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參數(shù)資料
| 型號： | LF3347QC12 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | CAP 1.0UF 63V METAL POLY |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 80K |
| 代理商： | LF3347QC12 |
DEVICES INCORPORATED
Video Imaging Products
LF3347
High-Speed Image Filter with Coefficient RAM
08/16/2000–LDS.3347-G
3
OCEN — Output Clock Enable
When OCEN is LOW, the output
register is enabled for data loading.
When OCEN is HIGH, output register
loading is disabled and the register’s
contents will not change.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed. If
ACC is LOW, no accumulation is
performed, the prior accumulated sum
is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging product is added
to the sum of the previous products.
LD — Load Control
LD enables the loading of data into the
coefficient banks and control registers
(control registers are the round and limit
registers). When LD is LOW, data on
CC
11-0
is latched into the device on the
rising edge of CCCLK. When LD is
HIGH, data cannot be loaded into the
coefficient banks and control registers.
When enabling the input circuitry for
data loading, the LF3347 requires a
HIGH to LOW transition of LD in order
to function properly. Therefore, LD
needs to be set HIGH immediately after
power up to ensure proper operation of
the input circuitry.
It takes five CCCLK clock cycles to load
one coefficient set into the four coefficient
banks or to load one control register.
When the input circuitry is enabled (LD
goes LOW), the first value loaded into the
device on CC
11-0
is an address which
determines what will be loaded (see
Table 2). The next four values loaded on
CC
11-0
is the data to be loaded into the
coefficient banks or control register (see
Tables 3-5). After the last data value is
loaded, another coefficient bank address
or control register may be loaded by
feeding another address into CC
11-0
.
When all desired coefficient banks and
control registers are loaded, the input
circuitry must be disabled by setting LD HIGH.
SELRND
3-0
— Round Select
SELRND
3-0
allows the user to select
which rounding register will be used
in the rounding circuit to round/ offset
the data.
SHIFT
4-0
— Shift
SHIFT
4-0
determines which 16-bits of
the 32-bits from the accumulator are
passed to the output (see Table 1).
SELLMT
3-0
— Limit Select
SELLMT
3-0
allows the user to control
which limiting register will be used in
the limiting circuit to set the upper
and lower limits on the data.
LMTEN — Limit Enable
When LMTEN is LOW, limiting is
enabled and the selected limit register
is used to determine the valid range of
output values for the overall filter.
When HIGH, limiting is disabled.
F
IGURE
2. R
OUNDING
, S
ELECTING
,
L
IMITING
C
IRCUITRY
RND
SELECT
LIMIT
32
16
LMTEN
32
SHIFT
4-0
ULMT
15-0
LLMT
15-0
RND
31-0
16
16
32
Register
Load Address
Bits
Register Description
A
7-0
SELRND
3-0
SELLMT
3-0
CS0
CS1
·
·
CS255
000H
001H
·
·
0FFH
11-0
11-0
·
·
11-0
Coefficient Set 0
Coefficient Set 1
·
·
Coefficient Set 255
00H
01H
·
·
FFH
RND0
RND1
·
·
RND15
800H
801H
·
·
80FH
31-0
31-0
·
·
31-0
Rounding Register 0
Rounding Register 1
·
·
Rounding Register 15
0 0 0 0
0 0 0 1
·
·
1 1 1 1
LMT0
LMT1
·
·
LMT15
C00H
C01H
·
·
C0FH
31-16/15-0
31-16/15-0
·
·
31-16/15-0
Upper / Lower Limit Register 0
Upper / Lower Limit Register 0
·
·
Upper / Lower Limit Register 15
0 0 0 0
0 0 0 1
·
·
1 1 1 1
T
ABLE
2.
R
EGISTER
F
ORMATS
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