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參數(shù)資料
| 型號： | LF3347QC12 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | CAP 1.0UF 63V METAL POLY |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 80K |
| 代理商： | LF3347QC12 |
DEVICES INCORPORATED
LF3347
High-Speed Image Filter with Coefficient RAM
2
Video Imaging Products
08/16/2000–LDS.3347-G
with an image resampling se-
quencer. Larger kernels or more
complex functions can be realized
by utilizing multiple devices.
Unrestricted access to all data
ports and addressable coefficient
banks provides the LF3347 with
considerable flexibility in applica-
tions such as digital filters, adap-
tive FIR filters, mixers, and other
similar systems requiring high-
speed processing.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must
be connected.
Clocks
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
CCCLK — Coefficient/Control Clock
When LD is LOW, the rising edge of
CCCLK latches data on CC
11-0
into the
device.
Inputs
D1
11-0
– D4
11-0
— Data Input
D1–D4 are the 12-bit registered data
input ports. Data is latched on the
rising edge of CLK.
A
7-0
— Row Address
A
7-0
determines which row in the
coefficient banks feed data to the
multipliers. A
7-0
is latched on the
rising edge of CLK. When a new
row address is loaded into the row
address register, data from the
coefficient banks will be latched into
the multiplier input registers on the
next rising edge of CLK.
CC
11-0
— Control/Coefficient Data Input
CC
11-0
is used to load data into the
coefficient banks and control regis-
ters. Data present on
CC
11-0
is
latched on the rising edge of CCCLK
when LD is LOW.
Outputs
S
15-0
— Data Output
S
15-0
is the 16-bit registered data
output port.
Controls
ENB
1
–ENB
4
— Data Input Enables
The ENB
N
(
N
= 1, 2, 3, or 4) inputs
allow the D
N
registers to be updated
on each clock cycle. When ENB
N
is
LOW, data on D
N11-0
is latched into
the D
N
register on the rising edge of
CLK. When ENB
N
is HIGH, data on
D
N11-0
is not latched into the D
N
register and the register contents
will not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on
each clock cycle. When ENBA is
LOW, data on A
7-0
is latched into
the row address register on the rising
edge of CLK. When ENBA is HIGH,
data on A
7-0
is not latched into the
row address register and the register
contents will not be changed.
OE — Output Enable
When OE is LOW, S
15-0
is enabled for
output. When OE is HIGH, S
15-0
is
placed in a high-impedance state.
F
IGURE
1.
I
NPUT
F
ORMATS
Data
T
ABLE
1.
O
UTPUT
F
ORMATS
SHIFT
4-0
S
15
S
14
S
13
· · ·
· · ·
· · ·
· · ·
S
8
S
7
· · ·
· · ·
· · ·
· · ·
S
2
S
1
S
0
00000
F
15
F
14
F
13
F
8
F
7
F
2
F
1
F
0
00001
F
16
F
15
F
14
F
9
F
8
F
3
F
2
F
1
00010
·
·
·
F
17
·
·
·
F
16
·
·
·
F
15
·
·
·
F
10
·
·
·
F
9
·
·
·
F
4
·
·
·
F
3
·
·
·
F
2
·
·
·
01110
F
29
F
28
F
27
· · ·
· · ·
· · ·
F
22
F
21
· · ·
· · ·
· · ·
F
16
F
15
F
14
01111
F
30
F
29
F
28
F
23
F
22
F
17
F
16
F
15
10000
F
31
F
30
F
29
F
24
F
23
F
18
F
17
F
16
11 10 9
–2
0
(Sign)
2
1
0
2
–1
2
–2
2
–9
2
–10
2
–11
11 10 9
–2
0
(Sign)
2
1
0
2
–1
2
–2
2
–9
2
–10
2
–11
11 10 9
–2
11
(Sign)
2
2
2
1
2
1
0
2
0
2
10
2
9
11 10 9
–2
11
(Sign)
2
2
2
1
2
1
0
2
0
2
10
2
9
Fractional Two's Complement
Integer Two's Complement
Coefficient
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