參數(shù)資料
型號(hào)： LC5521D
元件分類： 穩(wěn)壓器
英文描述： 2.5 A POWER FACTOR CONTROLLER, 18 kHz SWITCHING FREQ-MAX, DIP7
封裝： DIP-8/7
文件頁數(shù)： 30/40頁
文件大?。?/td> 888K
代理商： LC5521D
36
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28106.02
Determine the minimum switching frequency, f0, and the flyback
voltage, Ef, and then calculate the primary inductance, LP, as
follows:
=
LP
2 × PO× f0
1
( EIN(PK)(min) × DON)2
+ EIN(PK)(min)× × f0×DON× √CV
2
(17)
where
EIN(PK)(min) is the C2 peak voltage at minimum AC input
voltage VIN(AC)(min):
EIN(PK)(min) = √
2 × VIN(AC)(min) ×η2
(18)
η2 is the peak voltage decline percentage, approximately 0.9,
PO is the maximum output power:
PO = VO × IO
(19)
VO is the output voltage, IO is the maximum output current,
f0 is the minimum switching frequency,
η1 is the efficiency (80% to 90%),
CV is the voltage resonant capacitor (C3) capacitance
(47 to 470 pF),
DON is the duty cycle at AC minimum input:
DON = Ef / (EIN(PK)(min) + Ef )
(20)
Ef is the flyback voltage:
Ef = (NP /NS) × (EO +Vf)
(21)
NP and NS indicate the number of turns of the primary winding
and secondary winding, respectively;
Vf is the D8 forward voltage, approximately 0.7 V.
The drain peak current, IDP, and the drain peak current after duty
cycle compensation, I'DP, can be calculated by:
=
IIN(RMS)
Input rms current:
η1 × VIN(AC)(min)
PO
(22)
=
IDP
DON × η1 × η2 × VIN(AC)(min)
2√2 × PO
Drain peak current:
(23)
=
tONDLY
Quasi-resonant delay time:
√LP × CV
(24)
Maximum on duty after compensation:
D'ON = (1 – f0 × tONDLY) × DON
(25)
Drain peak current after compensation:
=
I''DP
D'ON × η1 × η2 × VAC(MIN)
2√2 × PO
(26)
In transformer design, AL-value and NP must be set in a way that
the ferrite core does not saturate. Here, use ampere turn value
(AT), the result of I''DP × NP and the graph of NI-Limit (AT)
versus AL-value (figure 51 is an example of it). NI-Limit is the
limit that the ampere turn value should not exceed; otherwise the
core saturates. So use the graph and formula 28, which expresses
the relationship of LP, AL-value, and NP to appropriately set
these values. In addition, target 30% below the NI-Limit curve as
a design margin in consideration of temperature effects and other
variations, as expressed by the formulas below:
=
NI-Limit
NP × I''DP × 130%
(27)
=
NP
LP
AL Value
(28)
Then, the rest of the winding turns are determined by the formu-
las below.
=
NS
Ef
VO + Vf × N
P
(29)
=
ND
VCC
VO + Vf
× N
S
(30)
Trace and Component Layout Design
Pay extra attention in trace design and component layout in order
to avoid malfunctioning and increases in noise and losses.
In general, high-current loop areas (shaded areas in figure 52)
should be small, and loop traces should be wide and short to
reduce series inductances. In addition, the earth ground line is
Figure 51. Example of NI-Limit versus AL-Value characteristics
Figure 52. High frequency current loops
NI
-Limit(A
T)
AL-Value(nH/T
2 )
Saturation region boundary
Margin=30%
Design point
(example)
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