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參數(shù)資料
| 型號： | L6260 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4.5 - 5.5V DISK DRIVER SPINDLE & VCM, POWER & CONTROL COMBO’S |
| 中文描述： | 4.5 - 5.5V的磁盤驅(qū)動程序主軸 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 305K |
| 代理商： | L6260 |
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CIRCUIT OPERATION
General
This device includes a sensorless spin driver,
VCM driver, power sequencing, actuator retrac-
tion with dynamic braking, serial interface for a
microprocessor and frequency locked loop for
speed control. The device is register based and
designed to operate via either 3V or 5V power
supply.
POR & UnderVoltage
The L6260 has an on chip power monitoring sys-
tem that controls all aspects of powering up,
Power On Reset of the Logic (POR), low voltage
detection and power down sequencing. The cir-
cuitry consists of a Bandgapreference generator,
hysteresis comparitor (for low voltage detection)
and a POR timer circuit (which controls the dura-
tionof the reset).
Four external pins determine the behavior of this
circuit.
UV1 & UV2: These two pins are provided to
the user to connect to the supply voltages for
low voltage detection. The voltage on these
pins is compared to the internal Bandgapvolt-
age to determineif a low voltage on one of the
supply pins has been detected.The comparitor
has built in hysteresis to reduce the effects of
noise on the supply lines triggering a false
POR. In other words, if either one of these in-
puts falls below 1.25V then the supply is re-
garded as being ”under voltage”. Normally one
of thesepins will be connectedto allow a sens-
ing of a 3V supply and the other to the 5V sup-
ply but thisis arbitrary
POR_DLY: This is a pin from which a capacitor
can be connected to ground. This sets the du-
ration of the reset state of the this chip. On
power up, an internal current source charges
the capacitor with a current of approximately
2mA. When the voltage on this pin reachesthe
bandgap voltage, the chip comes out of its re-
set state. The duration of this reset is deter-
mined by the size of an external capacitor to
ground.
POR: The POR pin is an output from the chip
for resettingother devices.
Frequency Locked Loop Fine Error Counter
(Reg 7)
This register contains the error detected between
the ”fine” counter value of the FLL and the actual
spindle rotation time (in either mechanical or elec-
trical mode).
Reg:
7
Name:
FLL Fine Error Counter Register
Type:
Read Only
BIT
0
1
2
3
4
5
6
7
8
9
10
11
LABEL
DESCRIPTION
@POR
0
0
0
0
0
0
0
0
0
0
0
0
FINEC BIT 0
FINEC BIT 1
FINEC BIT 2
FINEC BIT 3
FINEC BIT 4
FINEC BIT 5
FINEC BIT 6
FINEC BIT 7
FINEC BIT 8
FINEC BIT 9
FINEC BIT 10
FINEC BIT 11
FLL Fine error count LSB
FLL Fine error count MSB
L6260
14/30
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