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| 型號： | KXPC8240RVV250E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU INTEGRATED 250MHZ 352TBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 250MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
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MPC8240 Integrated Processor Hardware Specifications
17
Electrical and Thermal Characteristics
Figure 11. AC Test Load for the MPC8240
1.4.2.4.1
PCI Signal Output Hold Timing
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz
PCI systems, the MPC8240 has a programmable output hold delay for PCI signals. The initial value of the
output hold delay is determined by the values on the MCP and CKE reset configuration signals. Further
output hold delay values are available through programming the PCI_HOLD_DEL value of the PMCR2
configuration register.
14b
SDRAM_SYNC_IN to output high impedance (for all others)
—
4.0
ns
1
Notes:
1. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of
the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question.
SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode
(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 8.
2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD
of the signal in question for 3.3-V PCI signaling levels. See Figure 9.
3. All output timings assume a purely resistive 50-
load (see Figure 11). Output timings are measured at the pin;
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
4. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[0:3], PAR, TRDY, FRAME, STOP,
DEVSEL, PERR, SERR, AD[0:31], REQ[4:0], GNT[4:0], IDSEL, and INTA.
5. PCI hold times can be varied; see Section 1.4.2.4.1, “PCI Signal Output Hold Timing,” for information on
programmable PCI output hold times. The values shown for item 13a are for PCI compliance.
6. These specifications are for the default driver strengths indicated in Table 4.
Table 9. Output AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristic 3, 6
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2 for PCI
RL = 50
Pin
Output Measurements are Made at the Device Pin
GVDD/2 for Memory
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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