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| 型號： | KXPC8240RVV250E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU INTEGRATED 250MHZ 352TBGA |
| 標準包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 250MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應商設備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
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48
MPC8240 Integrated Processor Hardware Specifications
Document Revision History
0.6
Updated Technology in Section 1.3 from 0.32 to 0.29 m.
Updated Notes in Table 2. Changed line 2 to reflect supply voltage wording of the other lines. Changed
notes 2 and 3 to include all LVDD input tolerant signals.
Updated Table 4 eliminating LVDD = 5.0 V entries for DRV_PCI. Changed LVDD to OVDD for remaining
DRV_PCI entries. Updated notes.
Updated Table 6 to show minimum memory bus operating frequency is 33 MHz.
Updated Table 8 with new characterization data for numbers 22 and 23.
Updated Table 8 adding ‘/In-line’ to ‘Registered’ in Spec 10b2.
Updated Table 9 to Table 10 to how changes for MCP and CKE reset configuration changes for
PCI_HOLD_DEL.
Updated Table 12 eliminating 25 MHz column since memory interface does not operate at this frequency.
Updated Table 17:
REQ4/DA4 and PLL_CFG[0:4]/DA[10:6] changed Pin Type from Input to I/O.
DA2, DA[11:13], DA[14:15] changed Pin Type from I/O to Output.
Reversed vector ordering for the PCI Interface Signals: C/BE[0:3] changed to C/BE[3:0], AD[0:31]
changed to AD[31:0], GNT[0:3] changed to GNT[3:0], and REQ[0:3] changed to REQ[3:0]. The
package pin number orderings were also reversed meaning that pin functionality did NOT change. For
example, AD0 is still on signal C22, AD1 is still on signal D22, ... AD31 is still on signal V25. This
change was made to make the vectored PCI signals in the MPC8240 Hardware Specification
consistent with the PCI Local Bus Specification and the MPC8240 User Manual vector ordering.
Deleted Note 19 indicating LAVDD and AVDD are internally connected. Added a new Note 19 about
OSC_IN and EPIC control signals input voltage levels.
Updated Section 1.7.1, eliminating references to LAVDD and AVDD being internally connected.
Updated Table 23 changing 2-k
pull-up resistor on VDD_SENSE to 1-k.
Moved Section 1.7.7 to be at end of JTAG section.
Changed erroneous C4 reference in Figure 26 title to TBGA.
Deleted references to FLOTHERM models in Section 1.7.8.3.
1
Updated notes for Table 2, to include that the values maybe exceeded for up to 20 ms.
Updated Figure 2, removed note 2 concerning voltage sequencing.
Updated Solder Balls in Section 1.5.1, from 63/37 Sn/Pb to 62 Sn/36 Pb/2 Ag.
Updated Table 9, adding ‘a(chǎn)ddress’ to 12b1-3.
Updated Table 10 to show the settings for silicon rev. 1.0/1.1 and for silicon rev. 1.2/1.3.
Updated Table 17:
removed Note 10 from TRIG_OUT.
Created separate rows for TEST0 and TEST1 to reflect the change made in Note 1
Changed Note 1 to refer only to TEST0.
Removed Section 1.7.2.
Section 1.6.8—Updated list of heat sink and thermal interface vendors.
Changed format of Section 1.8.
2
Section 1.3.1.5—Updated Table 5 to reflect power numbers for the L spec (2.5 V) part. The power
numbers for the R spec (2.625 V) part are now in the part number specifications document
MPC8240RZUPNS.
Section 1.5—Table 18 now reflects the L spec parts (200 MHz). The R spec PLL table is now in the R spec
(250 MHz) part number specifications document MPC8240RZUPNS.
Section 1.6.6—Updated this section and Figure 26.
Section 1.8.2—Updated reference to part number specifications document.
Table 19. Document Revision History (continued)
Revision
Number
Substantive Change(s)
F
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S
e
m
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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