- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1932 > KXPC8240RVV250E (Freescale Semiconductor)IC MPU INTEGRATED 250MHZ 352TBGA PDF資料下載
參數(shù)資料
| 型號： | KXPC8240RVV250E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU INTEGRATED 250MHZ 352TBGA |
| 標準包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 250MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應商設備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
MPC8240 Integrated Processor Hardware Specifications
37
System Design Information
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8240. The trace length may be used to skew or adjust
the timing window as needed. See the Motorola application note AN1794, “Backside L2 Timing Analysis
for PCB Design Engineers,” for more information on this topic.
1.7.5
Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: DH[0:31], DL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0:31] and
PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be
driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the
system to minimize possible output switching.
The TEST0 pins require pull-up resistors of 120
or less connected to OV
DD.
It is recommended that TEST2 have a weak pull-up resistor (2–10 k
) connected to GV
DD.
It is recommended that the following signals be pulled up to OVDD with weak pull-up resistors (2–10 k
):
SDA, SCL, SMI, SRESET, TBEN, CHKSTOP_IN, and TEST1.
It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors
(2–10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, TRDY, and INTA. The resistor values
may need to be adjusted stronger to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0:3], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors enabled only while the MPC8240 is in the reset state:
GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and
QACK/DA0. See Table 17 for more information.
The following pins are reset configuration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], and PLL_CFG[0:4]/DA[10:6]. These pins are sampled during reset
to configure the device.
Reset configuration pins should be tied to GND via 1-k
pull-down resistors to ensure a logic 0 level is read
into the configuration bits during reset if the default logic 1 level is not desired.
Any other unused active-low input pins should be tied to a logic one level through weak pull-up resistors
(2–10 k
) to the appropriate power supply. Unused active-high input pins should be tied to GND through
weak pull-down resistors (2–10 k
).
1.7.6
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. While
it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| KXPC8260ZUIHBC | IC MPU POWERQUICC II 480-TBGA |
| LA4128V-75TN144E | IC CPLD 128MACROCELLS 144TQFP |
| LA72730-N-E | IC AUDIO/VIDEO SWITCH TV 24SDIP |
| LAMXO2280E-3FTN324E | IC FPGA AUTO 2.28KLUTS 324-BGA |
| LC51024VG-75F676I | IC XPLD 1024MC 7.5NS 676FPBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KXPC8250AZUPHBA | 制造商:Motorola Inc 功能描述: |
| KXPC8255CVVIFBC | 功能描述:微處理器 - MPU PQ 2 HIP 3 NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KXPC8255CZUIFBC | 功能描述:微處理器 - MPU POWERQUICC II HIP3 REV C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KXPC8255VVIFBC | 功能描述:微處理器 - MPU PQ 2 HIP 3 NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KXPC8255ZUIFBC | 功能描述:微處理器 - MPU POWERQUICC II HIP3 REV C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復。