參數(shù)資料
型號: KSZ8995XA-EVAL
廠商: Micrel Inc
文件頁數(shù): 34/51頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8995XA
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8995XA
主要屬性: 5 個(gè)端口,100BASE-TX/100BASE-FX/10BASE-T
次要屬性: 2xMII,SNI
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱: 576-1642
KS8995XA
Micrel, Inc.
M9999-051305
4
May 2005
Table of Contents
System Level Applications .............................................................................................................................................................. 6
Pin Description (by Number) ........................................................................................................................................................... 8
Pin Description (by Name) ............................................................................................................................................................ 13
Pin Configuration ........................................................................................................................................................................... 18
Introduction
............................................................................................................................................................................ 19
Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19
100BASE-TX Transmit ............................................................................................................................................................ 19
100BASE-TX Receive ............................................................................................................................................................. 19
PLL Clock Synthesizer ............................................................................................................................................................ 19
Scrambler/De-scrambler (100BASE-TX only) ......................................................................................................................... 19
100BaseFX Operation ............................................................................................................................................................. 19
100BaseFX Signal Detection ................................................................................................................................................... 20
100BaseFX Far End Fault ....................................................................................................................................................... 20
10BASE-T Transmit ................................................................................................................................................................. 20
10BASE-T Receive .................................................................................................................................................................. 20
Power Management ................................................................................................................................................................ 20
MDI/MDI-X Auto Crossover ..................................................................................................................................................... 20
Auto-Negotiation ...................................................................................................................................................................... 20
Functional Overview: Switch Core ............................................................................................................................................... 21
Address Look Up ..................................................................................................................................................................... 21
Learning
............................................................................................................................................................................ 21
Migration
............................................................................................................................................................................ 21
Aging
............................................................................................................................................................................ 21
Switching Engine ..................................................................................................................................................................... 21
MAC (Media Access Controller) Operation ............................................................................................................................. 22
Inter-Packet Gap ............................................................................................................................................................. 22
Backoff Algorithm ............................................................................................................................................................ 22
Late Collision .................................................................................................................................................................. 22
Illegal Frame ................................................................................................................................................................... 22
Flow Control .................................................................................................................................................................... 22
Half-Duplex Back Pressure ............................................................................................................................................. 22
Broadcast Storm Protection ............................................................................................................................................ 23
MII Interface Operation .................................................................................................................................................................. 23
SNI Interface Operation ................................................................................................................................................................. 25
Advanced Functionality ................................................................................................................................................................. 25
QoS Support ............................................................................................................................................................................ 25
Rate Limit Support ................................................................................................................................................................... 27
Configuration Interface ............................................................................................................................................................ 28
I2C Master Serial Bus Configuration ............................................................................................................................... 28
MII Management Interface (MIIM) .................................................................................................................................................. 28
Register Map
............................................................................................................................................................................ 29
Global Registers ...................................................................................................................................................................... 29
Register 0 (0x00): Chip ID0 ............................................................................................................................................ 29
Register 1 (0x01): Chip ID1/Start Switch ....................................................................................................................... 29
Register 2 (0x02): Global Control 0 ................................................................................................................................ 29
Register 3 (0x03): Global Control 1 ................................................................................................................................ 30
Register 4 (0x04): Global Control 2 ................................................................................................................................ 31
Register 5 (0x05): Global Control 3 ................................................................................................................................ 31
Register 6 (0x06): Global Control 4 ................................................................................................................................ 32
Register 7 (0x07): Global Control 5 ................................................................................................................................ 32
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