參數(shù)資料
型號(hào)： KSZ8995XA-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 21/51頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8995XA
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8995XA
主要屬性： 5 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T
次要屬性： 2xMII，SNI
已供物品： 板，CD，文檔，電源
產(chǎn)品目錄頁(yè)面： 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱(chēng)： 576-1642
KS8995XA
Micrel, Inc.
M9999-051305
28
May 2005
Configuration Interface
The KS8995XA functions as a unmanaged switch. If no EEPROM exists, the KS8995XA will operate from its default and strap-
in settings.
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, the KS8995XA can perform more advanced features like broadcast storm protection and rate
control. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the memory
map, except the status registers. The configuration access time (t
prgm) is less than 15ms as shown in Figure 10.
....
RST_N
SCL
SDA
t
prgm<15 ms
Figure 10. EEPROM Configuration Timing Diagram
To configure the KS8995XA with a pre-configured EEPROM use the following steps:
At the board level, connect pin 110 on the KS8995XA to the SCL pin on the EEPROM. Connect pin 111 on the
KS8995XA to the SDA pin on the EEPROM.
Be sure the board-level reset signal is connected to the KS8995XA reset signal on pin 115 (RST_N).
Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other data
will be ignored.
Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KS8995XA. After the reset is de-asserted, the KS8995XA will begin reading configuration data from the EEPROM.
The configuration access time (t
prgm) is less than 15ms.
Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995XA. An external device with MDC/MDIO capability
is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard, please reference the IEEE
802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995XA. It can only access the standard MII registers. See “MIIM Registers” section.
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