參數(shù)資料
型號(hào)： KSZ8995XA-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 20/51頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR KSZ8995XA
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8995XA
主要屬性： 5 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T
次要屬性： 2xMII，SNI
已供物品： 板，CD，文檔，電源
產(chǎn)品目錄頁(yè)面： 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱(chēng)： 576-1642
May 2005
27
M9999-051305
KS8995XA
Micrel, Inc.
DiffServ Field (Binary)
Code Point
KS8995X (Reg. and Bit)
000000
DSCP[0]
0x67, bit 0
000001
DSCP[1]
0x67, bit 1
000010
DSCP[2]
0x67, bit 2
000011
DSCP[3]
0x67, bit 3
000100
DSCP[4]
0x67, bit 4
111011
DSCP[59]
0x60, bit 3
111100
DSCP[60]
0x60, bit 4
111101
DSCP[61]
0x60, bit 5
111110
DSCP[62]
0x60, bit 6
111111
DSCP[63]
0x60, bit 7
Table 5. DiffServ Code Point
Once classification of the packets has been determined either by port-based priority, 802.1p tag-based priority or DiffServ
priority, they are placed in either the high or low priority queue on the egress port. The user can enable the egress priority queues
on a per port basis by setting bit 0 of registers 0x10, 0x20, 0x30, 0x40, and 0x50 for ports 1, 2, 3, 4 and 5, respectively. If the
egress priority queue for a given port is not set, the port will treat all packets as if they are the same priority, even though packets
are classified on their ingress ports. If the egress priority queue for a given port is enabled, packets are serviced based on the
user programmable egress policy. The priority scheme selection is set in register 0x05 bits[3-2] as shown in Table 6.
Register
0x05, bit 3
0x05, bit 2
Egress Priority Scheme
00
Always deliver high priority packets first
01
Deliver high/low priority packets at a ratio of 10/1
10
Deliver high/low priority packets at a ratio of 5/1
11
Deliver high/low priority packets at a ratio of 2/1
Table 6. Transmit Priority Ratio
The KS8995XA offers support for port-based, 802.1p tag-based, and IPv4 DiffServ priority, as well as programmable egress
policies. These KS8995XA QoS features enable identifying, classifying and forwarding packets based on their priority. The
system designer is able to use this device to build network elements that give more control over system resources, priority
service to mission critical applications, and can be integrated into the next generation of multimedia networks.
Rate Limit Support
KS8995XA supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports rate
limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps.
The KS8995XA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate
limit mechanism starts to count the number of bytes during this interval.
For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the
“one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed
greater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the rate
limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered.
For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until
the “one second” interval expires.
If priority is enabled, the KS8995XA can support different rate controls for both high priority and low priority packets. This can
be programmed through Registers 21 – 27.
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