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參數(shù)資料
型號: KSZ8995XA-EVAL
廠商: Micrel Inc
文件頁數(shù): 2/51頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8995XA
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8995XA
主要屬性: 5 個(gè)端口,100BASE-TX/100BASE-FX/10BASE-T
次要屬性: 2xMII,SNI
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱: 576-1642
KS8995XA
Micrel, Inc.
M9999-051305
10
May 2005
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
63
PMRXD2
Ipd/O
5
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
64
PMRXD1
Ipd/O
5
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
65
PMRXD0
Ipd/O
5
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
66
PMRXER
Ipd/O
5
PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes.
67
PCRS
Ipd/O
5
PHY[5] MII carrier sense/force duplex mode. See “Register 28.”
68
PCOL
Ipd/O
5
PHY[5] MII collision detect/force flow control. See “Register 18.”
69
SMTXEN
Ipd
Switch MII transmit enable.
70
SMTXD3
Ipd
Switch MII transmit bit 3.
71
SMTXD2
Ipd
Switch MII transmit bit 2.
72
SMTXD1
Ipd
Switch MII transmit bit 1.
73
SMTXD0
Ipd
Switch MII transmit bit 0.
74
SMTXER
Ipd
Switch MII transmit error.
75
SMTXC
I/O
Switch MII transmit clock. PHY or MAC mode MII.
76
GNDD
Gnd
Digital ground.
77
VDDIO
P
3.3V digital V
DD for digital I/O circuitry.
78
SMRXC
I/O
Switch MII receive clock. PHY or MAC mode MII.
79
SMRXDV
Ipd/O
Switch MII receive data valid.
80
SMRXD3
Ipd/O
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
81
SMRXD2
Ipd/O
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode.
82
SMRXD1
Ipd/O
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
83
SMRXD0
Ipd/O
Switch MII receive bit 0; Strap option: see “Register 11[1].”
84
SCOL
Ipd/O
Switch MII collision detect.
85
SCRS
Ipd/O
Switch mode carrier sense.
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated.
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