參數(shù)資料
型號: KSZ8995XA-EVAL
廠商: Micrel Inc
文件頁數(shù): 1/51頁
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8995XA
標準包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8995XA
主要屬性: 5 個端口,100BASE-TX/100BASE-FX/10BASE-T
次要屬性: 2xMII,SNI
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關產(chǎn)品: KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱: 576-1642
May 2005
1
M9999-051305
KS8995XA
Micrel, Inc.
KS8995XA
Integrated 5-Port 10/100 QoS Switch
Rev. 2.3
General Description
The KS8995XA is a highly integrated Layer-2 quality of
service (QoS) switch with optimized bill of materials (BOM)
cost for low port count, cost-sensitive 10/100Mbps switch
systems. It also provides an extensive feature set including
three different QoS priority schemes, a dual MII interface for
BOM cost reduction, rate limiting to offload CPU tasks,
software and hardware power-down, a MDC/MDIO control
interface and port mirroring/monitoring to effectively address
both current and emerging Fast Ethernet applications.
The KS8995XA contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five media access
control (MAC) units, a high-speed non-blocking switch fabric,
a dedicated address lookup engine, and an on-chip frame
buffer memory.
All PHY units support 10BASE-T and 100BASE-TX. In addi-
tion, two of the PHY units support 100BaseFX (Ports 4 and 5).
Features
Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
Shared memory based switch fabric with fully non-
blocking configuration
10BASE-T, 100BASE-TX and 100BASE-FX modes
(FX in Ports 4 and 5)
Dual MII configuration: MII-Switch (MAC or PHY
mode MII) and MII-P5 (PHY mode MII)
VLAN ID tag/untag options, per-port basis
Enable/disable option for huge frame size up to
1916 bytes per frame
Broadcast storm protection with percent control –
global and per-port basis
Optimization for fiber-to-copper media conversion
Full-chip hardware power-down support (register
configuration not saved)
Per-port-based software power-save on PHY
(idle link detection, register configuration preserved)
QoS/CoS packets prioritization supports: per port,
802.1p and DiffServ-based
Micrel, Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
Functional Diagram
1K Look-Up
Engine
Queue
Mgmnt
10/100
MAC 1
Buffer
Mgmnt
Frame
Buffers
FIFO
,Flo
w
Contro
l,
VLAN
T
agging,
P
rior
ity
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
EEPROM
I/F
LED I/F
Auto
MDI/MDI-X
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MII-P5
MDC, MDI/O
KS8995XA
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
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