hbwhelp@micrel.com or (408) 955-1690 Registers 104 to" />
參數(shù)資料
型號(hào): KSZ8993FL
廠商: Micrel Inc
文件頁數(shù): 75/100頁
文件大小: 0K
描述: IC CONV MED 10/100 SGL 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-1035
Micrel, Inc.
KS8993F/FL
June 2009
76
M9999-062509
hbwhelp@micrel.com or (408) 955-1690
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address
for MAC pause control frames.
Register 104 (0x68): MAC Address Register 0
Bit
Name
R/W
Description
Default
7-0
MACA[47:40]
R/W
0x00
Register 105 (0x69): MAC Address Register 1
Bit
Name
R/W
Description
Default
7-0
MACA[39:32]
R/W
0x10
Register 106 (0x6A): MAC Address Register 2
Bit
Name
R/W
Description
Default
7-0
MACA[31:24]
R/W
0xA1
Register 107 (0x6B): MAC Address Register 3
Bit
Name
R/W
Description
Default
7-0
MACA[23:16]
R/W
0xFF
Register 108 (0x6C): MAC Address Register 4
Bit
Name
R/W
Description
Default
7-0
MACA[15:8]
R/W
0xFF
Register 109 (0x6D): MAC Address Register 5
Bit
Name
R/W
Description
Default
7-0
MACA[7:0]
R/W
0xFF
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic MAC address
table, or the MIB counters.
Register 110 (0x6E): Indirect Access Control 0
Bit
Name
R/W
Description
Default
7-5
Reserved
R/W
Reserved
000
4
Read High
Write Low
R/W
= 1, read cycle
= 0, write cycle
0
3-2
Table select
R/W
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
00
1-0
Indirect
address high
R/W
Bit [9-8] of indirect address
00
Register 111 (0x6F): Indirect Access Control 1
Bit
Name
R/W
Description
Default
7-0
Indirect
address low
R/W
Bit [7-0] of indirect address
0000_0000
Note: A write to reg. 111 will actually trigger a command. Read or write access will be decided by bit 4 of reg. 110.
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