參數(shù)資料
型號： KSZ8862-16MQL-FX
廠商： Micrel Inc
文件頁數(shù)： 92/125頁
文件大小： 0K
描述： IC SWITCH ETH 2P 16BIT 128PQFP
標準包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
69
M9999-040407-3.0
Bank 32 Switch ID and Enable Register (0x00): SIDER
This register contains the switch ID and the switch enable control.
Bit
Default
R/W
Description
15-8
0x88
RO
Family ID
Chip family ID
7-4
0x8
RO
Chip ID
0x8 is assigned to KSZ8862M
3-1
0x1
RO
Revision ID
0
RW
Start Switch
1 = start the chip.
0 = switch is disabled.
Bank 32 Switch Global Control Register 1 (0x02): SGCR1
This register contains the global control for the switch function.
Bit
Default
R/W
Description
15
0
RW
Pass All Frames
1 = switch all packets including bad ones. Used solely for debugging purposes. Works in
conjunction with Sniffer mode only.
14
0
RW
Reserved
13
1
RW
IEEE 802.3x Transmit Direction Flow Control Enable
1 = enables transmit direction flow control feature.
0 = will not enable transmit direction flow control feature. The switch will not generate any flow
control packets.
12
1
RW
IEEE 802.3x Receive Direction Flow Control Enable
1 = enables receive direction flow control feature.
0 = will not enable receive direction flow control feature. The switch will not react to any received
flow control packets.
11
0
RW
Frame Length Field Check
1 = checks frame length field in the IEEE packets. If the actual length does not match, the packet
will be dropped (for Length/Type field < 1500).
10
1
RW
Aging Enable
1 = enable age function in the chip.
0 = disable age function in the chip.
9
0
RW
Fast Age Enable
1 = turn on fast age (800us).
8
0
RW
Aggressive Back-Off Enable
1 = enable more aggressive back off algorithm in half-duplex mode to enhance performance. This
is not an IEEE standard.
7-4
-
RW
Reserved
3
0x0
RW
Pass Flow Control Packet
1 = switch will not filter 802.1x “flow control” packets.
2-1
-
RW
Reserved
0
RW
Link Change Age
1 = link change from “l(fā)ink” to “no link” will cause fast aging (<800us) to age address table faster.
After an age cycle is complete, the age logic will return to normal (300 + 75 seconds).
Note: If any port is unplugged, all addresses will be automatically aged out.
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