參數(shù)資料
型號: KSZ8851-16MQL
廠商: Micrel Inc
文件頁數(shù): 3/88頁
文件大?。?/td> 0K
描述: IC CTLR MAC/PHY NON-PCI 128-PQFP
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-3292-ND - BOARD EVALUATION KSZ8851-16MLL
其它名稱: 576-3253
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
August 2009
11
M9999-083109-2.0
Pin Description for 16-Bit
Pin Number
Pin Name
Type
Pin Function
1
TEST_EN
Ipd
Test Enable
For normal operation, open or pull-down this pin to ground.
2
SCAN_EN
Ipd
Scan Test Scan Mux Enable
For normal operation, open or pull-down this pin to ground.
3
P1LED2
Opu
4
P1LED1
Ipu/O
5
P1LED0
Ipu/O
Port 1 LED indicators
1 defined as follows:
LED is ON when output is LOW; LED is OFF when output is HIGH.
Chip Global Control Register: CGCR
bit [15,9]
[0,0] Default
[0,1]
P1LED3
2
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
Reg. CGCR bit [15,9]
[1,0]
[1,1]
P1LED3
2
Act
P1LED2
Link
P1LED1
Full duplex/Col
P1LED0
Speed
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
6
NC
No Connect.
7
NC
No Connect.
8
NC
No Connect.
9
DGND
Gnd
Digital ground
10
VDDIO
P
3.3V, 2.5V or 1.8V digital VDDIO input power supply for IO with well decoupling capacitors.
11
NC
No Connect.
12
NC
No Connect.
13
NC
No Connect.
14
PME
Ipu/O
Power Management Event: It is asserted (low or high depends on polarity set in PMECR
register) when one of the wake-on-LAN events is detected by KSZ8851M. The
KSZ8851M is requesting the system to wake up from low power mode.
15
NC
No Connect.
16
INTRN
Opu
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set.
17
LDEVN
Opu
Local Device Not
Active Low output signal, asserted when AEN is Low and A7-A1 decode to the
KSZ8851M right address register. LDEVN is a combinational decode of the Address and
AEN signal.
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