參數(shù)資料
型號(hào): KSZ8851-16MQL
廠商: Micrel Inc
文件頁數(shù): 24/88頁
文件大小: 0K
描述: IC CTLR MAC/PHY NON-PCI 128-PQFP
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-3292-ND - BOARD EVALUATION KSZ8851-16MLL
其它名稱: 576-3253
2009 Microchip Technology Inc.
DS39682E-page 29
PIC18F45J10 FAMILY
3.4
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 3-1).
FIGURE 3-4:
PLL BLOCK DIAGRAM
MUX
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
FIN
FOUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
÷4
HS or EC
Mode
REGISTER 3-1:
OSCTUNE: PLL CONTROL REGISTER
U-0
R/W-0
U-0
—PLLEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6
PLLEN:
Frequency Multiplier PLL Enable bit(1)
1
= PLL enabled
0
= PLL disabled
bit 5-0
Unimplemented:
Read as ‘0’
Note 1:
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads
as ‘0’.
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