參數(shù)資料
型號(hào): KSZ8851-16MQL
廠商: Micrel Inc
文件頁(yè)數(shù): 18/88頁(yè)
文件大?。?/td> 0K
描述: IC CTLR MAC/PHY NON-PCI 128-PQFP
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 66
控制器類(lèi)型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
配用: 576-3292-ND - BOARD EVALUATION KSZ8851-16MLL
其它名稱(chēng): 576-3253
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
August 2009
25
M9999-083109-2.0
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 3.01k
Ω (1%)
resistor for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX
driver.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
PLL Clock Synthesizer (Recovery)
The internal PLL clock synthesizer can generate either 125MHz, 62.5MHz, 41.66MHz, or 25MHz clocks by setting the on-
chip bus control register (0x20) for KSZ8851M system timing. These internal clocks are generated from an external
25MHz crystal or oscillator.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler
generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same
sequence as at the transmitter.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents are
at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and
a phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with
levels less than 400mV or with short pulse widths to prevent noise at the RXP1 or RXM1 input from falsely triggering the
decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851M decodes a
data frame. The receiver clock is maintained active during idle periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8851M supports HP-Auto MDI/MDI-X and
IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for
the KSZ8851M device. This feature is extremely useful when end users are unaware of cable types in addition to saving
on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control
registers. The IEEE 802.3u standard MDI and MDI-X definitions are as below:
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KSZ8851-16MQL-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓:
KSZ8851-16MQLI 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free, I-Temp) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851-32MQL 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851-32MQLI 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface (I-Temp) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8851MLL 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Single Port MAC/PHY Controller with Non PCI Interface