參數(shù)資料
型號： KS57P21832
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： CMOS technology provides for low power consumption and a wide operating voltage range.
中文描述： CMOS技術(shù)提供了低功耗和寬工作電壓范圍。
文件頁數(shù)： 20/34頁
文件大?。?/td> 274K
代理商： KS57P21832
ELECTRICAL DATA
KS57C21832/P21832
14-8
Table 14-7. A.C. Electrical Characteristics
(T
A
= - 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Time
(note)
Symbol
t
CY
Conditions
Min
0.67
Typ
–
Max
64
Units
μs
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.0 V to 5.5 V
V
DD
= 2.7 V to 5.5 V
0.95
64
TCL0, TCL1 Input
Frequency
f
TI0,
f
TI1
0
–
1.5
MHz
V
DD
= 2.0 V to 5.5 V
V
DD
= 2.7 V to 5.5 V
1
TCL0, TCL1 Input
High, Low Width
t
TIH0,
t
TIL0
t
TIH1,
t
TIL1
0.48
–
–
μs
V
DD
= 2.0 V to 5.5 V
V
DD
= 2.7 V to 5.5 V; Input
1.8
SCK
Cycle Time
t
KCY
800
–
–
ns
Internal
SCK
source; Output
V
DD
= 2.0 V to 5.5 V; Input
650
3200
Internal
SCK
source; Output
V
DD
= 2.7 V to 5.5 V; Input
3800
325
SCK
High, Low
Width
t
KH
, t
KL
–
–
ns
Internal
SCK
source; Output
t
KCY
/2-
50
1600
V
DD
= 2.0 V to 5.5 V; Input
Internal
SCK
source; Output
t
KCY
/2
-
150
100
SI Setup Time to
SCK
High
t
SIK
V
DD
= 2.7 V to 5.5 V; Input
–
–
ns
V
DD
= 2.7 V to 5.5 V; Output
V
DD
= 2.0 V to 5.5 V; Input
V
DD
= 2.0 V to 5.5 V; Output
V
DD
= 2.7 V to 5.5 V; Input
150
150
500
SI Hold Time to
SCK
High
t
KSI
400
–
–
ns
V
DD
= 2.7 V to 5.5 V; Output
V
DD
= 2.0 V to 5.5 V; Input
V
DD
= 2.0 V to 5.5 V; Output
400
600
500
NOTE:
Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
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