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參數(shù)資料
| 型號： | KM4232W259A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CMOS Window RAM（1M Byte Dual Ported DRAM Array）(CMOS視窗RAM（1M字節(jié)的雙口動態(tài)RAM陣列）) |
| 中文描述： | 窗口的CMOS內(nèi)存（1M字節(jié)雙端口內(nèi)存陣列）（視窗的CMOS存儲器（100萬字節(jié)的雙口動態(tài)內(nèi)存陣列）） |
| 文件頁數(shù)： | 3/46頁 |
| 文件大?。?/td> | 836K |
| 代理商： | KM4232W259A |
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KM4232W259A
CMOS WINDOW RAM
Rev.0 (August 1997)
PIN DESCRIPTION
*1 EDO : Extended Data Out
SYMBOL
TYPE
DESCRIPTION
SC
INPUT
Serial Clock :
Clock input to the serial address counter for the SAM registers.
The serial access is initiated from SC rising edge.
Output data is held until the next clock rising edge.
SE
SQ
0
- SQ
15
BE
0
-
3
INPUT
OUTPUT
INPUT
Serial Port Enable :
SE enables the serial output buffers.
Serial Output :
Output pins of the 128 x 16 Serial data register.
Byte Enable :
These signals enables the random output buffer during read operation or the write
driver during write operation. They are latched on the falling edge of CAS.
BE
0
controls W
0
/DQ
0
- W
7
/DQ
7
.
OE
INPUT
Output Enable :
Enables the random output buffer when dropped LOW after CAS goes Low.
Otherwise the output is in a High-Z state. On the falling edge of RAS, OE=HIGH indicates new
mask data will be used for the operation. If OE=LOW, previously loaded mask data is used.
RAS
INPUT
Row Address Strobe :
It acts as a master chip enable clock, also serves as a clock to latch the
row address(A
0
- A
8
). It also latches the mask data for bit plane mask when OE is HIGH at RAS
falling edge. CAS before RAS refresh mode is available if falling edge of RAS is preceded by
CAS=LOW.
CAS
INPUT
Column Address Strobe :
Used as a clock, which latches the column address(A
0
- A
8
) and
determines the functionality of mixed mode by monitoring DSF status. It can also initiate the
read(EDO*1) or write access to the selected words and transfer the selected data(256 bits) to the
SAM register.
DSF0, 1, 2
INPUT
Special Function Select :
The DSF0, 1, 2 data latched by CAS falling edge is used to indicate
which special functions, Block Write, Internal Move, LCR, LMR Split Read Transfer, Ultra fast
page mode read(EDO) and write cycles, are going to be performed.
W
0
/DQ
0
-
W
31
/DQ
31
INPUT
OUTPUT
Input and Output pin to the RAM :
These pins carry read, write or mask data, depending upon
the type of cycle. Refer to RAS and CAS control cycles truth tables.
A
0
- A
8
INPUT
Address Input :
The KM4232W259A utilizes a multiplexed addressing method for selecting one
word among 256K words of memory cells, 9 row addresses and 9 column addresses are latched
by the RAS and CAS falling edges. Some address pins can be used as control signals in particu-
lar cycles(e.g. A
0
for LMR cycle, A
0
, A
1
for LCR, UFBW8, SRT/SRTR cycles, and A
0
and A
1
can
address the latches during UFBR, UFBWL cycles).
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