KM4132G271A
CMOS SGRAM
Rev.0 (August 1997)
I/O(=DQ)
31 24
Blue
1 1 0 0 0 0 1 1
23 16
Green
1 1 1 0 0 0 0 1
15 8
Yellow
0 0 0 0 1 1 1 1
7 0
Red
1 0 1 0 0 0 1 1
Color Register
DQMi
DQM
3
=0
1 1 1 1 1 1 1 1
Yellow
0 0 0 0 1 1 1 1
DQM
2
=0
1 1 0 1 1 1 0 1
Yellow
0 0 0 0 1 1 1 1
DQM
1
=0
0 1 0 0 0 0 1 0
Green
1 1 1 0 0 0 0 1
DQM
0
=1
0 1 1 1 0 1 1 0
White
0 0 0 0 0 0 0 0
Mask Register
Before Write
After Write
Blue
1 1 0 0 0 0 1 1
Blue
1 1 0 0 0 0 1 1
Red
1 0 1 0 0 0 1 1
White
0 0 0 0 0 0 0 0
(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"
i) STEP
¨
SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011,1110,0001,0000,1111,1010,0011"
¨è
SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110"
--> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Maskin g
¨é
Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable
¨ê
Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110" (Pixel Mask)
i) ILLUSTRATION
Note 2
Note 1
I/O(=DQ)
DQMi
Color Register
31 24
DQM
3
=0
Color3=Blue
Yellow DQ
24
=H
Yellow DQ
25
=H
Yellow DQ
26
=H
Yellow DQ
27
=L
Yellow DQ
28
=H
Yellow DQ
29
=H
Yellow DQ
30
=H
Yellow DQ
31
=L
Blue
Blue
Blue
Yellow
Blue
Blue
Blue
Yellow
23 16
DQM
2
=0
Color2=Green
Yellow DQ
16
=H
Yellow DQ
17
=H
Yellow DQ
18
=H
Yellow DQ
19
=H
Yellow DQ
20
=H
Yellow DQ
21
=H
Yellow DQ
22
=H
Yellow DQ
23
=H
Blue
Blue
Blue
Blue
Blue
Blue
Blue
Blue
15 8
DQM
1
=0
Color1=Yellow
Green DQ
8
=H
Green DQ
9
=L
Green DQ
10
=H
Green DQ
11
=L
Green DQ
12
=H
Green DQ
13
=L
Green DQ
14
=H
Green DQ
15
=L
Red
Green
Red
Green
Red
Green
Red
Green
7 0
DQM
0
=1
Color0=Red
White DQ
0
=L
White DQ
1
=H
White DQ
2
=H
White DQ
3
=H
White DQ
4
=L
White DQ
5
=H
White DQ
6
=H
White DQ
7
=H
White
White
White
White
White
White
White
White
Before
Block
Write
&
DQ
(Pixel
data)
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
After
Block
Write
1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A
2-
0(000-111).
At block write, instead of ignored address A
2-0
, DQ
0-31
control each pixel.
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
Note 1
*Note :