參數(shù)資料
型號(hào)： KM29N16000ATS
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲(chǔ)器)
中文描述： 200萬(wàn)× 8位NAND閃存（2米× 8位的NAND閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 4/21頁(yè)
文件大小： 252K
代理商： KM29N16000ATS
KM29N16000ATS
FLASH MEMORY
4
PRODUCT INTRODUCTION
The KM29N16000A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pa ges
formed by one NAND structures, totaling 264 NAND structures of 16 cells. The array organization is shown in Figure 2. The progra m
and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array consist s
of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29N16000A.
The KM29N16000A has addresses multiplexed into 8 I/O
′
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written throug h
I/O
′
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : co l-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29N16000A.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Sequential Data Input
80h
-
Read 1
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
10h
-
Block Erase
60h
D0h
Read Status
70h
-
O
相關(guān)PDF資料
PDF描述
KM29N32000IT 4M x 8 Bit NAND Flash Memory(4M x 8位 NAND閃速存儲(chǔ)器)
KM29N32000T 4M x 8 Bit NAND Flash Memory(4M x 8位 NAND閃速存儲(chǔ)器)
KM29N32000TS 4M x 8 Bit NAND Flash Memory(4M x 8位 NAND閃速存儲(chǔ)器)
KM29U128IT 16M x 8 Bit NAND Flash Memory
KM29U128T 16M x 8 Bit NAND Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM29U128IT 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory
KM29U128T 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory
KM29U64000IT 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory
KM29U64000T 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory
KM29V16000AIT 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FLASH MEMORY
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*