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參數(shù)資料
| 型號(hào)： | KM29N16000ATS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲(chǔ)器) |
| 中文描述： | 200萬× 8位NAND閃存（2米× 8位的NAND閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 252K |
| 代理商： | KM29N16000ATS |
KM29N16000ATS
FLASH MEMORY
20
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin
is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
Rp =
V
CC
open drain output
Device
GND
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
Σ
I
L
=
Note*
8mA
+
Σ
I
L
where I
L
is the sum of the input currents of all devices tied to the
R/B pin.
*Note: KM29V16000A : 3.2V
KM29N16000A : 5.1V
KM29W16000A : 5.1V When Vcc=3.6V~5.5V
3.2V When Vcc=2.7V~3.6V
R/B
Figure 11. AC Waveforms for Power Transition
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage dete ctor
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
IL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
V
CC
WP
High
≈
≈
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