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參數(shù)資料
| 型號： | K8S1215EZC-SC1C0 |
| 元件分類： | PROM |
| 英文描述： | 32M X 16 FLASH 1.8V PROM, 100 ns, PBGA64 |
| 封裝： | 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 9/83頁 |
| 文件大?。?/td> | 1511K |
| 代理商： | K8S1215EZC-SC1C0 |
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K8S1215E(T/B/Z)C
datasheet NOR FLASH MEMORY
Rev. 1.1
9.5 Output Driver Setting
The device supports four kinds of output driver setting for matching the system characteristics. The users can tune the output driver impedance of the
data and RDY outputs by address bits A21-A19. (See Configuration Register Table) Table 13 shows which output driver would be tuned and the strength
according to A21-A19. Upon power-up or reset, the register will revert to the default setting.
[Table 13]
Output Driver setting Table
9.6 Autoselect Mode
By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read
mode. The system can then read autoselect codes from the internal register (which is separate from the memory array). Standard asynchronous read
cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition,
this mode allows the host system to verify the block protection or unprotection. Table 14 shows the address and data requirements. The autoselect com-
mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block
address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiat-
ing another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write
Reset command(F0H) into the command register.
[Table 14] Autoselect Mode Description
9.7 Standby Mode
When the CE inputs is held at VCC
± 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption.
In this mode, the device outputs are placed in the high impedance state, independent of the OE input. When the device is in either of these standby
modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or pro-
gramming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specifica-
tion.
9.8 Automatic Sleep Mode
The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses
remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE, WE
and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device provides
new data without wait time. Automatic sleep mode current is equal to standby mode current.
9.9 Output Disable Mode
When the OE input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
Address Bits
Value
Function
A21-A19
000
Driver Multiplier : 1/3
001
Driver Multiplier : 1/2
010
Reserve
011
Reserve
100
Driver Multiplier : 1 (default)
101
Reserve
110
Reserve
111
Driver Multiplier : 1.5
Description
Address
Read Data
Manufacturer ID
(DA) + 00H
ECH
Device ID
(DA) + 01H
Top boot(3010H), Bottom boot(3011H), Uniform block(3012H)
Block Protection/Unprotection
(BA) + 02H
01H (protected), 00H (unprotected)
Handshaking
(DA) + 03H
0H : handshaking, 1H : non-handshaking
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