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參數(shù)資料
| 型號： | K8S1215EZC-SC1C0 |
| 元件分類： | PROM |
| 英文描述： | 32M X 16 FLASH 1.8V PROM, 100 ns, PBGA64 |
| 封裝： | 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 8/83頁 |
| 文件大?。?/td> | 1511K |
| 代理商： | K8S1215EZC-SC1C0 |
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K8S1215E(T/B/Z)C
datasheet NOR FLASH MEMORY
Rev. 1.1
9.4.3. RDY Configuration
By default, the RDY pin will be high whenever there is valid data on the output. (RDY can be low active by Extended configuration register A11 setting :
RDY low indicates data valid) The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting.
The RDY pin behaves same way in word boundary crossing case.
[Table 10] Burst Mode Configuration Register Table
NOTE :
Initial wait state should be set according to it’s clock frequency. Table 10 recommend the program wait state for each clock frequencies.
Not 100% tested
[Table 11]
Extended Configuration Register Table
NOTE :
Default mode is asynchronous read mode. (A13=0, A12=0) In this mode device is still in asynchronous read even if it is in CLK rising while AVD low condition.
To use synchronous read mode, user should set Extended Configuration Register (A13=0, A12=1). In this mode both of asynchronous and synchronous read mode is available.
The synchronous (burst) mode should be started on the last rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A13=0, A12=1.
[Table 12]
Burst Address Sequences
Address Bit
Function
Settings (Binary)
A21
Output Driver Control
000 = setting 0
001 = setting 1
010 = setting 2 (Reserve)
011 = setting 3 (Reserve)
100 = setting 4 (default)
101 = setting 5 (Reserve)
110 = setting 6 (Reserve)
111 = setting 7
A20
A19
A18
RDY Active
0 = RDY active with data (default)
1 = RDY active one clock cycle before data
A17
Burst Read Mode
000 = Continuous (default)
001 = 8-word linear with wrap
010 = 16-word linear with wrap
011 ~ 111 = Reserve
A16
A15
A14
Programmable Wait State
0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH
0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*)
0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*)
0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*)
0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*)
0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*)
0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*)
0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*)
1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*)
1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default)
1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH
1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH
1100 ~1111 = Reserve
A13
A12
A11
Address Bit
Function
Settings (Binary)
A13
Read Mode
00 = Asynchronous Read Mode (default)
01 = Synchronous Burst Read Mode
10 ~ 11 = Reserve
A12
A11
RDY Polarity
0 = RDY signal is active high (default)
1 = RDY signal is active low
Start
Addr.
Burst Address Sequence
Continuous Burst
8-word Burst
16-word Burst
Wrap
0
0-1-2-3-4-5-6...
0-1-2-3-4-5-6-7
0-1-2-3 ... -D-E-F
1
1-2-3-4-5-6-7...
1-2-3-4-5-6-7-0
1-2-3-4 ... -E-F-0
2
2-3-4-5-6-7-8...
2-3-4-5-6-7-0-1
2-3-4-5 ... -F-0-1
.
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