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參數(shù)資料
| 型號(hào)： | K7I643684M-FC20 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 190K |
| 代理商： | K7I643684M-FC20 |
2Mx36 & 4Mx18 & 8Mx8 DDRII CIO b4 SRAM
- 10 -
Rev 0.1
Mar. 2003
K7I643684M
K7I641884M
K7I640884M
Preliminary
ABSOLUTE MAXIMUM RATINGS*
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
PARAMETER
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
VDD
-0.5 to 2.9
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
-0.5 to V DD
V
Voltage on Input Pin Relative to VSS
V IN
-0.5 to VDD+0.3
V
Power Dissipation
PD
TBD
W
Storage Temperature
TSTG
-65 to 150
°C
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V
±0.1V , TA=0°C to +70°C)
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5) for 175
≤ RQ ≤ 350.
3. |IOL|=(VDDQ/2)/(RQ/5) for 175
≤ RQ ≤ 350.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ .
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is V REF
±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=
-0.3V, V IL (Min)AC=-1.5V(pulse width
≤ 3ns).
10. VIH (Max)DC=
VDDQ +0.3, V IH (Max)AC= VDDQ +0.85V(pulse width
≤ 3ns).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
NOTES
Input Leakage Current
IIL
VDD=Max ; VIN=VSS to VDDQ
-2
+2
A
Output Leakage Current
IOL
Output Disabled,
-2
+2
A
Operating Current (x36): DDR
ICC
VDD=Max , IOUT=0mA
Cycle Time
≥ tKHKH Min
-30
-
TBD
mA
1,5
-25
-
-20
-
-16
Operating Current (x18): DDR
ICC
VDD=Max , IOUT=0mA
Cycle Time
≥ tKHKH Min
-30
-
TBD
mA
1,5
-25
-
-20
-
-16
-
Operating Current (x8): DDR
ICC
VDD=Max , IOUT=0mA
Cycle Time
≥ tKHKH Min
-30
-
TBD
mA
1,5
-25
-
-20
-
-16
Standby Current(NOP): DDR
ISB1
Device deselected, I OUT=0mA,
f=Max,
All Inputs
≤0.2V or ≥ VDD-0.2V
-30
-
TBD
mA
1,6
-25
-
-20
-
-16
-
Output High Voltage
VOH1
VDDQ/2-0.12 VDDQ/2+0.12
V
2,7
Output Low Voltage
VOL1
VDDQ/2-0.12 VDDQ/2+0.12
V
3,7
Output High Voltage
VOH2
IOH=-1.0mA
VDDQ -0.2
VDDQ
V
4
Output Low Voltage
VOL2
IOL=1.0mA
VSS
0.2
V
4
Input Low Voltage
VIL
-0.3
VREF-0.1
V
8,9
Input High Voltage
VIH
VREF+0.1
VDDQ+0.3
V
8,10
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