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參數(shù)資料
| 型號： | K7I643684M-FC20 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 190K |
| 代理商： | K7I643684M-FC20 |
2Mx36 & 4Mx18 & 8Mx8 DDRII CIO b4 SRAM
- 9 -
Rev 0.1
Mar. 2003
K7I643684M
K7I641884M
K7I640884M
Preliminary
WRITE TRUTH TABLE(x18)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices. x8 device operation is similar except that NW0 controls D0:D3 and NW 0 controls D4:D7.
K
BW0
BW1
OPERATION
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
H
L
WRITE BYTE 1 ( K
↑ )
↑
H
L
WRITE BYTE 1 ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
WRITE TRUTH TABLE(x36)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑ ).
3. Assumes a WRITE cycle was initiated.
K
BW0
BW 1
BW2
BW 3
OPERATION
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
WRITE ALL BYTEs ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
L
H
WRITE BYTE 0 ( K
↑ )
↑
H
L
H
WRITE BYTE 1 ( K
↑ )
↑
H
L
H
WRITE BYTE 1 ( K
↑ )
↑
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
↑
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
↑
H
WRITE NOTHING ( K
↑ )
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don
′t Care".
2. The rising edge of clock is symbolized by (
↑ ).
K
LD
R/W
Q
OPERATION
Q(A0)
Q(A1)
Q(A2)
Q(A3)
Stopped
X
Previous
state
Previous
state
Previous
state
Previous
state
Clock Stop
↑
H
X
High-Z
No Operation
↑
L
H
QOUT at
C(t+1)
QOUT at
C(t+2)
Q OUT at
C(t+2)
QOUT at
C(t+3)
Read
↑
L
Din at K(t+1)
Din at K(t+2)
Write
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| K7I643684M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
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