參數(shù)資料
型號(hào)： K7I643684M-FC20
元件分類： SRAM
英文描述： 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 11/18頁(yè)
文件大?。?/td> 190K
代理商： K7I643684M-FC20
2Mx36 & 4Mx18 & 8Mx8 DDRII CIO b4 SRAM
- 2 -
Rev 0.1
Mar. 2003
K7I643684M
K7I641884M
K7I640884M
Preliminary
2Mx36-bit, 4Mx18-bit, 8Mx8-bit DDRII CIO b4 SRAM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Pipelined, double-data rate operation.
Common data input/output bus .
HSTL I/O
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 4-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write (x18, x36) and nybble(x8) write function.
Simple depth expansion with no data contention.
Programmable output impedance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7I643684M-FC30
3.3
0.45
ns
K7I643684M-FC25
4.0
0.45
ns
K7I643684M-FC20
5.0
0.45
ns
K7I643684M-FC16
6.0
0.50
ns
X18
K7I641884M-FC30
3.3
0.45
ns
K7I641884M-FC25
4.0
0.45
ns
K7I641884M-FC20
5.0
0.45
ns
K7I641884M-FC16
6.0
0.50
ns
X8
K7I640884M-FC30
3.3
0.45
ns
K7I640884M-FC25
4.0
0.45
ns
K7I640884M-FC20
5.0
0.45
ns
K7I640884M-FC16
6.0
0.50
ns
LD
ADDRESS
R/W
C
ADD REG
&
BURST
LOGIC
DATA
REG
CLK
GEN
CTRL
LOGIC
2Mx36
(4Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
BWX
4(or 2)
DQ
SELECT OUTPUT CONTROL
S
E
N
S
E
A
M
P
S
W
R
IT
E
/R
E
A
D
E
C
O
D
E
O
U
T
P
U
T
R
E
G
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
D
R
IV
E
R
Notes: 1. Numbers in ( ) are for x18 device, x8 device also the same with appropriate adjustments of depth and width.
19
19 (or 20)
36 (or 18)
72
(Echo Clock out)
CQ, CQ
36 (or 18)
A0,A1
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung te chnology.
(or 20)
(or 36)
相關(guān)PDF資料
PDF描述
K8S1215EZC-SC1C0 32M X 16 FLASH 1.8V PROM, 100 ns, PBGA64
K8S5515ETC-SC1E0 16M X 16 FLASH 1.8V PROM, 100 ns, PBGA44
K9E2G08U0M-YIB00 256M X 8 FLASH 2.7V PROM, 30 ns, PDSO48
KA-59-281 TNC CONNECTOR, PLUG
KA-91-02 RF STRAIGHT ADAPTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K7I643684M-FC25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I643684M-FC30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I643684M-FCI16 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I643684M-FCI20 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I643684M-FECI25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
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