參數(shù)資料
型號: ISP1760BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù): 91/105頁
文件大?。?/td> 449K
代理商: ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
91 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
14.2 DMA timing
In the following sections:
Polarity of DACK is active HIGH
Polarity of DREQ is active HIGH.
14.2.1
Single cycle: DMA read
Fig 15. DMA read (single cycle).
Table 95:
V
CC(I/O)
= 1.65 V to 1.95 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a14
DACK assertion time after DREQ assertion
t
a24
RD_N assertion time after DACK assertion
t
d14
data valid time after RD_N assertion
t
w14
RD_N pulse width
t
a34
DREQ deassertion time after RD_N assertion
t
a44
DREQ deassertion to next DREQ assertion time -
DMA read (single cycle)
Min
0
0
-
t
d14
23
Max
-
-
24
-
-
56
Unit
ns
ns
ns
ns
ns
ns
Table 96:
V
CC(I/O)
= 3.3 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a14
DACK assertion time after DREQ assertion
t
a24
RD_N assertion time after DACK assertion
t
d14
data valid time after RD_N assertion
t
w14
RD_N pulse width
t
a34
DREQ deassertion time after RD_N assertion
t
a44
DREQ deassertion to next DREQ assertion time -
DMA read (single cycle)
Min
0
0
-
t
d14
11
Max
-
-
20
-
-
56
Unit
ns
ns
ns
ns
ns
ns
004aaa530
DATA
DREQ
DACK
RD_N
t
a14
t
a24
t
d14
t
w14
t
a44
t
a34
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