參數(shù)資料
型號: ISP1760BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù): 36/105頁
文件大?。?/td> 449K
代理商: ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
36 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
[2]
These fields read logic 0, if the PP (Port Power) bit in register PORTSC1 is logic 0.
8.2.8
ISO PTD Done Map register (R: 0130h)
The bit description of the register is given in
Table 24
.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
PO
1
R/W
5
12
PP
0
R/W
4
11
10
9
8
PIC[1:0]
LS[1:0]
reserved
[1]
0
R/W
1
ECSC
0
R/W
PR
0
R
0
0
R
7
0
R
6
0
0
R/W
3
R/W
2
PED
0
R/W
0
R/W
FPR
0
R/W
reserved
[1]
0
R/W
ECCS
0
R
0
0
R/W
R/W
Table 23:
Bit
31 to 20
19 to 16
PORTSC1 register: bit description
Symbol
Description
[1]
-
reserved
PTC[3:0]
Port Test Control
: When this field is zero, the port is not operating in a
test mode. A non-zero value indicates that it is operating in test mode
indicated by the value.
PIC[1:0]
Port Indicator Control
: Writing to this field has no effect if the
P_INDICATOR bit in the HCSPARAMS register is logic 0.
For a description on how these bits are implemented, refer to Universal
Serial Bus Specification Rev. 2.0
[2]
PO
Port Owner
: This bit unconditionally goes to logic 0 when the configured
bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This
bit unconditionally goes to logic 1 whenever the configured bit is logic 0.
PP
Port Power
: The function of this bit depends on the value of the PPC (Port
Power Control) field in the HCSPARAMS register.
LS[1:0]
Line Status
: This field reflect the current logical levels of the DP (bit 11)
and DM (bit 10) signal lines.
-
reserved
PR
Port Reset
: Logic 1 means the port is in the reset state. Logic 0 means
the port is not in reset.
[2]
SUSP
Suspend
: Logic 1 means the port is in the suspend state. Logic 0 means
the port is not suspended.
[2]
FPR
Force Port Resume
: Logic 1 means resume detected or driven on the
port. Logic 0 means no resume (K-state) detected or driven on the port.
[2]
-
reserved
PED
Port Enabled/Disabled
: Logic 1 means enable. Logic 0 means disable.
[2]
ECSC
Connect Status Change
: Logic 1 means change in ECCS. Logic 0
means no change.
[2]
ECCS
Current Connect Status
: Logic 1 indicates a device is present on the
port. Logic 0 indicates no device is present.
[2]
15 to 14
13
12
11 to 10
9
8
7
6
5 to 3
2
1
0
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