參數(shù)資料
型號: ISP1760BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù): 51/105頁
文件大?。?/td> 449K
代理商: ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
51 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.4.2
Interrupt Enable register (R/W: 0314h)
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Table 56
.
7
INT_IRQ
INT IRQ
: Indicates that an IRQ was asserted because an INT PTD was
completed, or the PTDs corresponding to the bits set in the INT IRQ
Mask AND or INT IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of INT PTDs
1 —
IRQ asserted because of completing INT PTD.
For details, see
Section 7.4
.
CLKREADY
Clock Ready
: Indicates that an IRQ was asserted as the internal clock
signals are running stable. Useful after a power-on or wake-up cycle.
0 —
No CLKREADY event has occurred
1 —
INT generated because of a CLKREADY event.
HC_SUSP
Host Controller Suspend
: Indicates that the Host Controller has
entered suspend mode.
0 —
No INT generated because of the Host Controller entering suspend
mode
1 —
INT generated because of the Host Controller entering suspend
mode.
If the ISR accesses the ISP1760, it will wake up for the time specified in
bits 31 to 16 of the Power Down Control register.
-
reserved; write logic 0
DMAEOT
INT
0 —
DMA transfer is not complete
1 —
IRQ asserted because the DMA transfer is complete.
-
reserved; write logic 0
SOFITLINT
SOT ITL Interrupt
:
0 —
No SOF event has occurred
1 —
An SOF event has occurred.
6
5
4
3
DMA EOT Interrupt
: Indicates DMA transfer completion.
2 to 1
0
Table 55:
Bit
Interrupt register: bit description
…continued
Symbol
Description
Table 56:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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