參數(shù)資料
型號： ISP1760BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù)： 53/105頁
文件大?。?/td> 449K
代理商： ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
53 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.4.3
ISO IRQ Mask OR register (R/W: 0318h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
Table 58
for bit description. For details,
see
Section 7.4
.
8.4.4
INT IRQ Mask OR register (R/W: 031Ch)
Each bit of this register (see
Table 59
) corresponds to one of the 32 INT PTDs defined,
and is a hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
8.4.5
ATL IRQ Mask OR register (R/W: 0320h)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
Table 60
for bit description. For details,
see
Section 7.4
.
4
3
-
DMAEOT
INT_E
reserved; write logic 0
DMA EOT Interrupt Enable
: Controls assertion of IRQ on the DMA
transfer completion.
0 —
No IRQ will be generated after the DMA transfer is completed
1 —
IRQ will be asserted because of the DMA transfer completion.
reserved; must be written with logic 0
SOT ITL Interrupt Enable
: Controls the IRQ generation at every SOF
occurrence.
0 —
No IRQ will be generated on an SOF occurrence
1 —
IRQ will be asserted at every SOF.
2 to 1
0
-
SOFITLINT
_E
Table 57:
Bit
Interrupt Enable register: bit description
…continued
Symbol
Description
Table 58:
Bit
31 to 0 ISO_IRQ_
MASK_OR
[31:0]
ISO IRQ Mask OR register: bit description
Symbol
Access Value
R/W
0000 0000h
Description
ISO IRQ Mask OR
: Represents a direct map for
ISO PTDs 31 to 0.
0 —
No OR condition defined between ISO PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain OR condition.
Table 59:
Bit
31 to 0 INT_IRQ_
MASK_OR
[31:0]
INT IRQ Mask OR register: bit description
Symbol
Access
Value
R/W
0000 0000h
Description
INT IRQ Mask OR
: Represents a direct map for
INT PTDs 31 to 0.
0 —
No OR condition defined between INT PTDs
31 to 0
1 —
The bits corresponding to certain PTDs are
set to logic 1 to define a certain OR condition.
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