參數(shù)資料
型號: ISP1760BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數(shù): 25/105頁
文件大?。?/td> 449K
代理商: ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
25 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Figure 7
shows the most commonly used power supply connection.
7.9 Power-on reset (POR)
When V
CC(5V0)
is directly connected to the RESET_N pin, the internal POR pulse width
(t
PORP
) will be typically 800 ns. The pulse is started when V
CC(5V0)
rises above V
TRIP
(1.2 V).
To give a better view of the functionality,
Figure 8
shows a possible curve of V
CC(5V0)
with
dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11
μ
s), the internal POR
pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the
detector will see the passing of the trip level and a delay element will add another t
PORP
before it drops to 0.
The internal POR pulse will be generated whenever V
CC(5V0)
drops below V
TRIP
for more
than 11
μ
s.
The RESET_N pin can be either connected to V
CC(I/O)
(using the internal POR circuit) or
externally controlled (by the microcontroller, ASIC, and so on).
Figure 9
shows the
availability of the clock with respect to the external POR.
Fig 7.
Most commonly used power supply connection.
004aaa534
V
CC(5V0)
, V
CC(I/O)
ISP1760
6, 7, 10,
40, 48, 59,
67, 75, 83,
94, 104, 115
V
REG(1V8)
85
10 μF
100 nF
100 nF
3.3 V
V
REG(1V8)
5, 50, 118
100 nF
V
REG(3V3)
9
10 μF
100 nF
(1) PORP = power-on reset pulse.
Fig 8.
Internal power-on reset timing.
004aaa584
V
CC(5V0)
t0
t1
t2
t3
t4
t5
V
TRIP
t
PORP
PORP
(1)
t
PORP
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