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參數(shù)資料
| 型號： | ISP1760BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus host controller for embedded applications |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128 |
| 文件頁數(shù)： | 38/105頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ISP1760BE |
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9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
38 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
This register represents a direct map of the done status of the 32 PTDs. The bit
corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is
completed. Reading the Done Map register will clear all the bits that are set to logic 1, and
the next reading will reflect the updated status of new executed PTDs.
8.2.12
INT PTD Skip Map register (R/W: 0144h)
Table 28
shows the bit description of the INT PTD Skip Map register.
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit
may be set. The information in that PTD is not processed. For example, NextPTDPointer
will not affect the order of processing of PTDs. The Skip bit should not be normally set on
the position indicated by NextPTDPointer.
8.2.13
INT PTD Last PTD register (R/W: 0148h)
The bit description of the register is given in
Table 29
.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed
(checking V = 1) in that PTD category. Subsequently, the process will restart with the first
PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective
memory space) would be checked, especially if only a few PTDs are defined. The
LastPTD bit must be normally set to a higher position than any other position indicated by
the NextPTDPointer from an active PTD.
8.2.14
ATL PTD Done Map register (R: 0150h)
Table 30
shows the bit description of the ATL PTD Done Map register.
This register represents a direct map of the done status of the 32 PTDs. The bit
corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is
completed. Reading the Done Map register will clear all the bits that are set to logic 1, and
the next reading will reflect the updated status of new executed PTDs.
8.2.15
ATL PTD Skip Map register (R/W: 0154h)
The bit description of the register is given in
Table 31
.
Table 28:
Bit
31 to 0
INT PTD Skip Map register: bit description
Symbol
Access
INT_PTD_SKIP_
MAP[31:0]
Value
FFFF FFFFh
Description
INT PTD Skip Map
: Skip map for each
of the 32 PTDs for the INT transfer
R/W
Table 29:
Bit
31 to 0
INT PTD Last PTD register: bit description
Symbol
Access
INT_PTD_LAST
_PTD[31:0]
Value
0000 0000h
INT PTD Last PTD
: Last PTD of the
32 PTDs as indicated by the 32 bitmap.
1h —
One PTD in INT
2h —
Two PTDs in INT
3h —
Three PTDs in INT.
Description
R/W
Table 30:
Bit
31 to 0 ATL_PTD_DONE
_MAP[31:0]
ATL PTD Done Map register: bit description
Symbol
Access
R
Value
0000 0000h
Description
ATL PTD Done Map
: Done map for
each of the 32 PTDs for the ATL transfer
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1760BE,518 | 功能描述:輸入/輸出控制器接口集成電路 USB HOST CONTROLLER RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| ISP1760BE,551 | 功能描述:輸入/輸出控制器接口集成電路 USB HS HOST CONTRLLR RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| ISP1760BE,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1760BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB HOST 128LQFP |
| ISP1760BEGA | 功能描述:IC USB CTRL HI-SPEED 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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