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參數(shù)資料
| 型號(hào)： | ISP1582BS,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC56 |
| 封裝： | 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56 |
| 文件頁數(shù)： | 44/69頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ISP1582BS,557 |
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ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
48 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you
do not need to issue the Unlock command because the microprocessor is powered and
therefore, the RD_N, WR_N and CS_N signals maintain their states.
When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are oating because the
microprocessor is not powered. To protect the ISP1582 registers from being corrupted
during suspend, register write is locked when the chip goes into suspend. Therefore, you
need to issue the Unlock command to unlock the ISP1582 registers.
8.5.6 Test Mode register (address: 84h)
This 1-byte register allows the rmware to set pins DP and DM to predetermined states for
testing purposes. The bit allocation is given in Table 71.
Remark: Only one bit can be set to logic 1 at a time. This must be implemented for the
Hi-Speed USB logo compliance testing. To exit test mode, power cycle is required.
[1]
Either FORCEHS or FORCEFS must be set at a time.
[2]
Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set at a time.
Reset
not applicable
Bus reset
not applicable
Access
WWWWWWWW
Bit
7
6
5
4
3
2
1
0
Table 70.
Unlock Device register: bit description
Bit
Symbol
Description
15 to 0
ULCODE[15:0]
Unlock Code: Writing data AA37h unlocks the internal registers
and FIFOs for writing, following a resume.
Table 71.
Test Mode register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FORCEHS
reserved
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
Reset
0
-
00000
Bus reset
unchanged
-
unchanged
0000
Access
R/W
-
R/W
Table 72.
Test Mode register: bit description
Bit
Symbol
Description
7
FORCEHS
Force High-Speed: Logic 1[1] forces the hardware to high-speed mode only
and disables the chirp detection logic.
6 to 5
-
reserved
4
FORCEFS
Force Full-Speed: Logic 1[1] forces the physical layer to full-speed mode
only and disables the chirp detection logic.
3
PRBS
Predetermined Random Pattern: Logic 1[2] sets pins DP and DM to toggle
in a predetermined random pattern.
2
KSTATE
K-State: Logic 1[2] sets pins DP and DM to the K state.
1
JSTATE
J-State: Logic 1[2] sets pins DP and DM to the J state.
0
SE0_NAK
SE0 NAK: Logic 1[2] sets pins DP and DM to a high-speed quiescent state.
The device only responds to a valid high-speed IN token with a NAK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1582BSGA | 功能描述:IC UBS CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1582BS-S | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS-T | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BSUM | 功能描述:IC USB PERIPH CONTROLLER 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1583 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed Universal Serial Bus peripheral controller |
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