參數(shù)資料
型號(hào): ISP1582BS,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 39/69頁
文件大?。?/td> 365K
代理商: ISP1582BS,557
ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
43 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
8.4.7 DMA Endpoint register (address: 58h)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in Table 57.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the rmware must not
reference the same endpoint on the Endpoint Index register.
8.4.8 DMA Burst Counter register (address: 64h)
Table 59 shows the bit allocation of the 2-byte register.
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
Reset
00000000
Bus reset
00000000
Access
R/W
Table 57.
DMA Endpoint register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
EPIDX[2:0]
DMADIR
Reset
----
0000
Bus reset
----
0000
Access
----
R/W
Table 58.
DMA Endpoint register: bit description
Bit
Symbol
Description
7 to 4
-
reserved
3 to 1
EPIDX[2:0]
Endpoint Index: Selects the indicated endpoint for DMA access
0
DMADIR
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA read transfers
1 — Selects the TX/IN FIFO for DMA write transfers
Table 59.
DMA Burst Counter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BURSTCOUNTER[12:8]
Reset
-
00000
Bus reset
-
00000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BURSTCOUNTER[7:0]
Reset
00000010
Bus reset
00000010
Access
R/W
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ISP1583 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed Universal Serial Bus peripheral controller