參數(shù)資料
型號(hào)： ISP1582BS,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝： 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁(yè)數(shù)： 20/69頁(yè)
文件大小： 365K
代理商： ISP1582BS,557
ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
26 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
[1]
No interrupt is designed for OTG. The VBUS interrupt, however, may assert as a side effect during the VBUS
pulsing (see note 2).
[2]
When OTG is in progress, the VBUS interrupt may be set because VBUS is charged over the VBUS sensing
threshold or the OTG host has turned on the VBUS supply to the device. Even if the VBUS interrupt is found
during SRP, the device must complete data-line pulsing and VBUS pulsing before starting the
B_SESSION_VALID detection.
[3]
OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it
must provide a switch circuit to supply power to the ISP1582 core during SRP.
Table 25.
OTG register: bit description
Bit
Symbo
l
Description[1][2][3]
7 to 6
-
reserved
5DP
Data Pulsing: Used for data-line pulsing to toggle DP to generate the required
data-line pulsing signal. The default value of this bit is logic 0. This bit must be
cleared when data-line pulsing is completed.
4
BSESS
VALID
B-Session Valid: The device can initiate another VBUS discharge sequence after
data-line pulsing and VBUS pulsing, and before it clears this bit and detects a
session valid.
This bit is latched to logic 1 once VBUS exceeds the B-device session valid
threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The
ISP1582 continuously updates this bit to logic 1 when the B-session is valid. If
the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1582).
0 — It implies that SRP has failed. To proceed to a normal operation, the device
can restart SRP, clear bit OTG or proceed to an error handling process.
1 — It implies that the B-session is valid. The device clears bit OTG, goes into
normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.
The OTG host has a maximum of 5 s before it responds to a session request.
During this period, the ISP1582 may request to suspend. Therefore, the device
rmware must wait for some time if it wishes to know the SRP result (success: if
there is minimum response from the host within 5 s; failure; if there is no
response from the host within 5 s).
3
INIT
COND
Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and
check the bit status. If it reads logic 0, it means that VBUS remains lower than
0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then
start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP
is violated. So, the device must abort SRP.
The bit is set to logic 1 by the ISP1582 when initial conditions are not met, and
only writing logic 1 clears the bit. (If initial conditions are not met after this bit has
been cleared, it will be set again).
Remark: This implementation does not cover the case if an initial SRP condition
is violated when this bit is read and data-line pulsing is started.
2
DISCV
Discharge VBUS: Set to logic 1 to discharge VBUS. The device discharges VBUS
before starting a new SRP. The discharge can take as long as 30 ms for VBUS to
be charged less than 0.8 V. This bit must be cleared (write logic 0) before
starting a session end detection.
1VP
VBUS Pulsing: Used for VBUS pulsing to toggle VP to generate the required VBUS
pulsing signal. This bit must be set for more than 16 ms and must be cleared
before 26 ms.
0OTG
On-The-Go:
1 — Enables the OTG function. The VBUS sensing functionality will be disabled.
0 — Normal operation. All OTG control bits will be masked. Status bits are
undened.
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