參數(shù)資料
型號: ISP1582BS,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 33/69頁
文件大小: 365K
代理商: ISP1582BS,557
ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
38 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
8.4.2 DMA Transfer Counter register (address: 34h)
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in Table 47.
For IN endpoint — Because there is a FIFO in the ISP1582 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when
it reaches zero.
Table 46.
DMA commands
Code
Name
Description
00h
GDMA Read
Generic DMA IN token transfer: Data is transferred from the external DMA bus to the
internal buffer. Strobe: DIOW by the external DMA controller.
01h
GDMA Write
Generic DMA OUT token transfer: Data is transferred from the internal buffer to the external
DMA bus. Strobe: DIOR by the external DMA controller.
02h to 0Dh
-
reserved
0Eh
Validate Buffer Validate Buffer (for debugging only): Request from the microcontroller to validate the
endpoint buffer, following a DMA-to-USB data transfer.
0Fh
Clear Buffer
Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a
DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer
is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This
bit is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two
times, that is, set and clear this bit two times.
10h
-
reserved
11h
Reset DMA
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK,
DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external
DMA controller. To prevent this, start the external DMA controller only after the DMA reset.
12h
-
reserved
13h
GDMA Stop
GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint
that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint
will be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of
the DMA Stop command.
Remark: For the DMA OUT transfer, if the DMA Burst Counter register is programmed to
some value, for example 512 bytes, and if a GDMA Stop command is issued in the middle of a
transfer, the transfer will continue until the end of the burst size (512 bytes). Issuing a GDMA
stop command does not allow the ISP1582 to stop in the middle of the burst. It can only be
stopped in between bursts.
14h to FFh
-
reserved
Table 47.
DMA Transfer Counter register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
DMACR4 = DMACR[31:24]
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ISP1583 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed Universal Serial Bus peripheral controller