參數(shù)資料
型號(hào)： ISP1582BS,557
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝： 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁(yè)數(shù)： 28/69頁(yè)
文件大小： 365K
代理商： ISP1582BS,557
ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
33 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer
Length register is not signicant. This register is useful only when transferring data that is
not a multiple of MaxPacketSize. The following two examples demonstrate the
signicance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be lled. This is because the
transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register must be lled with 62 bytes just
before the microprocessor writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use bit VENDP in the Control register if you are not using the Buffer Length register.
This is applicable only to the PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.
8.3.5 Buffer Status register (address: 1Eh)
This register is accessed using index. The endpoint index must rst be set before
accessing this register for the corresponding endpoint. It reects the status of the double
buffered endpoint FIFO.
Remark: This register is not applicable to the control endpoint.
Table 35.
Buffer Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATACOUNT[15:8]
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATACOUNT[7:0]
Reset
00000000
Bus reset
00000000
Access
R/W
Table 36.
Buffer Length register: bit description
Bit
Symbol
Description
15 to 0
DATACOUNT[15:0]
Data Count: Determines the current packet size of the indexed
endpoint FIFO.
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