參數(shù)資料
型號(hào)： ISP1561BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù)： 77/103頁(yè)
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
75 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.4.4 FRINDEX register (address: content of the base address register + 18h)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125
s, once each microframe. Bits N to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by system software in the FLS (Frame List Size) eld in the USBCMD register. This
register must be written as a DWORD. Byte writes produce undened results. This
register cannot be written unless the Host Controller is in the halted state, as indicated by
the HCH (HC Halted) bit. A write to this register while the RS (Run/Stop) bit is set
produces undened results. Writes to this register also affect the SOF value. The bit
allocation is given in Table 109.
2
PCIE
Port Change Interrupt Enable: When this bit and the PCD (Port
Change Detect) bit in the USBSTS register are set, the Host Controller
issues an interrupt. The interrupt is acknowledged by software
clearing the PCD (Port Change Detect) bit.
1
USB
ERRINTE
USB Error Interrupt Enable: When this bit and the USBERRINT bit in
the USBSTS register are set, the Host Controller issues an interrupt at
the next interrupt threshold. The interrupt is acknowledged by software
clearing the USBERRINT bit.
0
USBINTE
USB Interrupt Enable: When this bit and the USBINT bit in the
USBSTS register are set, the Host Controller issues an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing the USBINT bit.
Table 108. USBINTR register: bit description …continued
Bit
Symbol
Description
Table 109. FRINDEX register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FRINDEX[13:8]
Reset
00000000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FRINDEX[7:0]
Reset
00000000
Access
R/W
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