參數(shù)資料
型號(hào)： ISP1561BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù)： 13/103頁(yè)
文件大?。?/td> 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
17 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
Table 9.
Status register: bit description
Bit
Symbol
Description
15
DPE
Detected Parity Error: This bit must be set by the device whenever
it detects a parity error, even if the parity error handling is disabled.
14
SSE
Signaled System Error: This bit must be set whenever the device
asserts SERR#. Devices that never assert SERR# do not need to
implement this bit.
13
RMA
Received Master Abort: This bit must be set by a master device
whenever its transaction, except for special cycle, is terminated with
master abort. All master devices must implement this bit.
12
RTA
Received Target Abort: This bit must be set by a master device
whenever its transaction is terminated with target abort. All master
devices must implement this bit.
11
STA
Signaled Target Abort: This bit must be set by a target device
whenever it terminates a transaction with target abort. Devices that
never signal target abort do not need to implement this bit.
10 to 9
DEVSELT[1:0]
DEVSEL Timing: These bits encode the timing of DEVSEL#. There
are three allowable timing for assertion of DEVSEL#:
00b — for fast
01b — for medium
10b — for slow
11b — is reserved
These bits are read-only and must indicate the slowest time that a
device asserts DEVSEL# for any bus command, except
Conguration Read and Conguration Write.
8
MDPE
Master Data Parity Error: This bit is implemented by bus masters.
It is set when the following three conditions are met:
The bus agent asserted PERR# itself, on a read; or observed
PERR# asserted, on a write.
The agent setting the bit acted as the bus master for the
operation in which error occurred.
The Parity Error Response bit (in the Command register) is set.
7
FBBC
Fast Back-to-Back Capable: This read-only bit indicates whether
the target is capable of accepting fast back-to-back transactions
when the transactions are not to the same agent. This bit can be set
to logic 1 if the device can accept these transactions; and must be
set to logic 0 otherwise.
6
-
reserved
5
66MC
66 MHz Capable: This read-only bit indicates whether this device is
capable of running at 66 MHz. A value of logic 0 indicates 33 MHz,
and a value of logic 1 indicates 66 MHz.
4CL
Capabilities List: This read-only bit indicates whether this device
implements the pointer for a new capabilities linked list at offset 34h.
A value of logic 0 indicates that no new capabilities linked list is
available. A value of logic 1 indicates that the value read at offset
34h is a pointer in conguration space to a linked list of new
capabilities.
3 to 0
-
reserved
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