參數(shù)資料
型號： ISP1561BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù)： 18/103頁
文件大?。?/td> 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
21 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
8.2.1.14
Subsystem ID register (address: 2Eh)
Subsystem ID values are vendor-specic. The bit description of the Subsystem ID register
is given in Table 19.
[1]
X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.
8.2.1.15
Expansion ROM Base Address register (address: 30h)
Some PCI devices, especially those intended for use on expansion boards in the PC
architecture, require local EPROMs for expansion ROM. This 4-byte register at offset 30h
in a type 00h predened header is dened to handle the base address and size
information for this expansion ROM. The ISP1561 does not support expansion EPROM.
8.2.1.16
Capabilities Pointer register (address: 34h)
The Capabilities Pointer register is used to point to a linked list of new capabilities
implemented by the device. This register is only valid if the CL bit in the Status register is
set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software must
mask these bits off before using this register as a pointer in conguration space to the rst
entry of a linked list of new capabilities. The bit description of the register is given in
8.2.1.17
Interrupt Line register (address: 3Ch)
The Interrupt Line register is a 1-byte read/write register used to communicate interrupt
line routing information. This register must be implemented by any device or device
function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The
POST software needs to write the routing information into this register because it
initializes and congures the system. The bit description of the Interrupt Line register is
given in Table 21.
The value in this register species which input of the system interrupt controller(s) the
interrupt pin of the device is connected. The device itself does not use this value, rather it
is used by device drivers and operating systems to determine priority and vector
information. Values in this register are system architecture specic.
Table 19.
Subsystem ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
SID[15:0]
R
Subsystem ID: For the ISP1561, NXP Semiconductors has dened OHCI
functions as 1561h, and the EHCI function as 1562h.
Table 20.
Capabilities Pointer register: bit description
Bit
Symbol
Access
Value
Description
7 to 0
CP[7:0]
R
DCh
Capabilities Pointer: EHCI manages power efciently using this register. This
power management register is allocated at offset DCh. Only one Host
Controller is needed to manage power in the ISP1561.
Table 21.
Interrupt Line register: bit description
Bit
Symbol
Access
Value
Description
7 to 0
IL[7:0]
R/W
00h
Interrupt Line: Indicates which IRQ is used to report interrupt from the
ISP1561.
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