參數(shù)資料
型號(hào): ISP1501
英文描述: Hi-Speed Universal Serial Bus peripheral transceiver
中文描述: 高速通用串行總線外設(shè)收發(fā)器
文件頁(yè)數(shù): 19/40頁(yè)
文件大小: 770K
代理商: ISP1501
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
19 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
For HS chirp reception, the 16-bit data bus is in the bypass mode.
In the HS chirp mode, the receiver behaves like a simple serial to parallel converter.
The transition on DP and DM may be mapped to anywhere within the 16-bit word
boundary. Therefore, the output may not contain all 0s or 1s for one cycle. The SIE
samples the 16-bit parallel data to check for the presence of extended JKJK states.
RX_BS_ERROR no longer reflects a bit stuff error. The RX_VALID signal is used to
qualify the data. The RX_INACTIVE signal is used in the HS chirp receive state.
10.4 High-speed transmit path delay
The total transmit path maximum delay is 8 HS bit times at 480 MHz.
(1) Time interval controlled by the SIE.
Fig 17. HS chirp transmit timing.
handbook, full pagewidth
MGT200
40 to 60
μ
s(1)
0000H
HIGH
FFFFH
0000H
FFFFH
DATA[15:0]
TX_READY
TX_VALID
DP/DM
Fig 18. HS chirp receive timing.
handbook, full pagewidth
MGT201
40 to 60
μ
s
FFFFH
0000H
0000H
DATA[15:0]
RX_VALID
DP/DM
RX_INACTIVE
HS IDLE
HS IDLE
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