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參數(shù)資料
| 型號： | ISP1501 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral transceiver |
| 中文描述： | 高速通用串行總線外設收發(fā)器 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 770K |
| 代理商： | ISP1501 |
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Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
14 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
10. High-speed functionality
10.1 High-speed transmit
The ISP1501 must be set in high-speed state by setting MODE[1:0] = 02H.
High-speed data propagate to the DP and DM pins when the 16-bit input data bus is
driven. Driving pin DDIR to logic 1 switches the 16-bit data bus to input mode.
All data packets start with a 4-byte SYNC pattern and end with either a 1-byte or a
5-byte EOP (End of Packet). The SYNC pattern is a 32-bit pattern of KJKJKJKJ
KJKJKJKJ KJKJKJKJ KJKJKJKK, which is to be sent by the SIE as 0000H, 8000H to
the input. For a 1-byte EOP the HS pattern is generated with FEH. The 5-byte EOP
starts with FEH, followed by four bytes of FFH.
Remark:
All 16-bit data are sent LSB first.
When bit stuffing or the EOP finishes on an 8-bit boundary, the TX_BS_EN and
TX_LAST_BYTE determine the behavior of the ISP1501 is shown in
Table 7
.
(1) Implemented as part of the FS transceiver.
(2) Connected in FS state and HS chirp state.
Fig 8.
High-speed transceiver functional diagram.
MGT341
ISP1501
DP
DM
7
9
6
45
(1)
45
(1)
HS current
driver
HS current source enable
NRZI enable
BS enable
NRZI disable
BS disable
HS drive enable
HS data
HS differential
receiver
squelch
detection
circuit
squelch
sampling clock
sampling clock
sampling clock
TRANSMIT LOGIC
RECEIVE LOGIC
MUX
NRZI DECODER
BIT DE-STUFFING
1
R
PLL
BIT STUFFING
LSB
43
2
42
44
45
1
12, 11
38 to 31,
28 to 21
16
2
TX_READY
TX_VALID
TX_LAST_BYTE
TX_BS_EN
TEST_J_K
SUSPEND
MODE1, MODE0
DATA15
to
DATA0
shift
enable
NRZI ENCODER
ELASTIC FIFO
1
R
46
47
48
39
12
20
RX_BS_ERROR
RX_INACTIVE
RX_VALID
RX_LAST_BYTE
MODE1
DDIR
45
1
TEST_J_K
SUSPEND
1.5 k
±
5%
(2)
3.3 V
RPU
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