參數(shù)資料
型號: ISP1181BDGG,112
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 40/70頁
文件大?。?/td> 341K
代理商: ISP1181BDGG,112
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
45 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
16. Power-on reset
The ISP1181B has an internal power-on reset (POR) circuit. Input pin RESET can be
directly connected to VCC. The clock signal on output CLKOUT starts 0.5 ms after
power-on and normally requires 3 to 4 ms to stabilize.
The triggering voltage of the POR circuit is 2.0 V nominal. A POR is automatically
generated when VCC goes below the trigger voltage for a duration longer than 50 s.
A hardware reset disables all USB endpoints and clears all ECRs, except for the
control endpoint which is xed and always enabled. Section 9.3 explains how to
(re-)initialize the endpoints.
t1: clock is running
t2: BUS_CONF pins are sampled
t3: registers are accessible
(1) Supply voltage (5 V or 3.3 V), connected externally to pin RESET.
Fig 14. Power-on reset timing.
MGT026
t1
t2
t3
VCC (1)
2.0 V
0 V
≤ 350 s
> 50 s
1 ms
POR
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