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參數(shù)資料
| 型號： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 29/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
35 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.2.4
Validate Endpoint Buffer
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full ag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint see Section 9.5.
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none
12.2.5
Clear Endpoint Buffer
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
ag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see Section 9.5.
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
12.2.6
Check Endpoint Status
This command is used to check the status of the selected endpoint FIFO without
clearing any status or interrupt bits. The command accesses the Endpoint Status
Image Register, which contains a copy of the Endpoint Status Register. The bit
allocation of the Endpoint Status Image Register is shown in Table 33.
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Table 33:
Endpoint Status Image Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
00000000
Access
RRRRRRRR
Table 34:
Endpoint Status Image Register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
6
EPFULL1
A logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
A logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the next packet
(0 = DATA0 PID, 1 = DATA1 PID).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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