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參數(shù)資料
| 型號： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 10/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
18 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input
signals RD and WR are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW and MEMR signals: the RD and WR signals are also used as memory data
strobes.
10.4 End-Of-Transfer conditions
10.4.1
Bulk endpoints
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DMA Conguration Register, see Table 24):
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
External EOT: When reading from an OUT endpoint, an external EOT will stop the
DMA operation and clear any remaining data in the current FIFO. For a double-
buffered endpoint the other (inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data
packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to
the USB host at the next IN token.
DMA Counter Register: An EOT from the DMA Counter Register is enabled by
setting bit CNTREN in the DMA Conguration Register. The ISP1181B has a 16-bit
DMA Counter Register, which species the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DMA Counter Register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA
operation stops.
Fig 5.
ISP1181B in DACK-only DMA mode.
RAM
ISP1181B
DMA
CONTROLLER
CPU
DREQ
DACK
HRQ
HLDA
HRQ
HLDA
DREQ
DACK
RD
WR
004aaa138
AD0,
DATA1 to DATA15
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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