參數(shù)資料
型號(hào): ISP1181BDGG,112
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 32/70頁
文件大?。?/td> 341K
代理商: ISP1181BDGG,112
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
38 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.3.3
Write/Read Scratch Register
This command accesses the 16-bit Scratch Register, which can be used by the
rmware to save and restore information, for example, the device status before
powering down in ‘suspend’ state. The register bit allocation is given in Table 40.
Code (Hex): B2/B3 — write/read Scratch Register
Transaction — write/read 2 bytes
12.3.4
Read Frame Number
This command returns the frame number of the last successfully received SOF. It is
followed by reading one or two bytes from the Frame Number Register, containing the
frame number (lower byte rst). The Frame Number Register is shown in Table 42.
Remark: After a bus reset, the value of the Frame Number Register is undened.
Bit
7
6
5
4
3
2
1
0
Symbol
UNLOCKL[7:0] = 37H
Reset
00110111
Access
WWWWWWWW
Table 39:
Lock Register: bit description
Bit
Symbol
Description
15 to 0
UNLOCK[15:0]
Sending data AA37H unlocks the internal registers and FIFOs
for writing, following a ‘resume’.
Table 40:
Scratch Information Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
SFIRH[6:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
SFIRL[7:0]
Reset
00000000
Access
R/W
Table 41:
Scratch Information Register: bit description
Bit
Symbol
Description
15
-
reserved; must be logic 0
14 to 8
SFIRH[6:0]
Scratch Information Register (high byte)
7 to 0
SFIRL[7:0]
Scratch Information Register (low byte)
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