參數(shù)資料
型號(hào): ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 9/137頁
文件大?。?/td> 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
105 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.3.3
DcScratch register (R/W: B3H/B2H)
This command accesses the 16-bit DcScratch register, which can be used by the
rmware to save and restore information, e.g., the device status before powering
down in ‘suspend’ state. The register bit allocation is given in Table 101.
Code (Hex): B2/B3 — write/read Scratch register
Transaction — write/read 1 word
13.3.4
Read Frame Number (R: B4H)
This command returns the frame number of the last successfully received SOF. It is
followed by reading one word from the DcFrameNumber register, containing the
frame number. The DcFrameNumber register is shown in Table 103.
Remark: After a bus reset, the value of the DcFrameNumber register is undened.
Code (Hex): B4 — read frame number
Transaction — read 1 word
Bit
7
6
5
4
3
2
1
0
Symbol
UNLOCKL[7:0]
Reset
37H
Access
W
Table 100: Lock register: bit description
Bit
Symbol
Description
15 to 0
UNLOCK[15:0]
Sending data AA37H unlocks the internal registers and FIFOs
for writing, following a ‘resume’.
Table 101: DcScratch register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
SFIRH[4:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
SFIRL[7:0]
Reset
00H
Access
R/W
Table 102: DcScratch register: bit description
Bit
Symbol
Description
15 to 13
-
reserved; must be logic 0
12 to 0
SFIR[12:0]
Scratch Information register
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