參數(shù)資料
型號: ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 4/137頁
文件大?。?/td> 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
100 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command will cause unpredictable behavior of the
ISP1161A1 DC.
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum (M + 1) words (isochronous endpoint: N
≤ 1023,
bulk/interrupt endpoint: N
≤ 32)
The data in the endpoint FIFO must be organized as shown in Table 90. An example
of endpoint FIFO access is given Table 91.
Remark: There is no protection against writing or reading past a buffer’s boundary or
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
13.2.2
DcEndpointStatus register (R: 50H–5FH)
This command is used to read the status of an endpoint FIFO. The command
accesses the DcEndpointStatus register, the bit allocation of which is shown in
Table 92. Reading the DcEndpointStatus register will clear the interrupt bit set for the
corresponding endpoint in the DcInterrupt register (see Table 108).
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by
the Stall/Unstall commands and by the reception of a SETUP token (see
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Table 90:
Endpoint FIFO organization
Word #
Description
0 (lower byte)
packet length (lower byte)
0 (upper byte)
packet length (upper byte)
1 (lower byte)
data byte 1
1 (upper byte)
data byte 2
::
M = (N + 1)/2
data byte N
Table 91:
Example of endpoint FIFO access
A0
Phase
Bus lines
Word #
Description
1
command
D[7:0]
-
command code (00H to 1FH)
D[15:8]
-
ignored
0
data
D[15:0]
0
packet length
0
data
D[15:0]
1
data word 1 (data byte 2, data byte 1)
0
data
D[15:0]
2
data word 2 (data byte 4, data byte 3)
:
:::
:
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