參數(shù)資料
型號： ISP1161A1BM,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 134/137頁
文件大?。?/td> 599K
代理商： ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
95 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The DcHardwareConguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin congurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read DcHardwareConguration register
Transaction — write/read 1 word
Table 82:
DcHardwareConguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
Reset
00100011
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DAKOLY
DRQPOL
DAKPOL
EOTPOL
WKUPCS
PWROFF
INTLVL
INTPOL
Reset
01000000
Access
R/W
Table 83:
DcHardwareConguration register: bit description
Bit
Symbol
Description
15
-
reserved
14
EXTPUL
A logic 1 indicates that an external 1.5 k
pull-up resistor is
used on pin D
+ and that SoftConnect is not used. Bus reset
value: unchanged.
13
NOLAZY
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
± 50 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the DcMode register. Bus reset value: unchanged.
12
CLKRUN
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
DcMode register. Bus reset value: unchanged.
11 to 8
CLKDIV[3:0]
This eld species the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 / (N + 1). The clock frequency range is
3 MHz to 48 MHz (N=0to 15) with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
7
DAKOLY
A logic 1 selects DACK-only DMA mode. A logic 0 selects
8237 compatible DMA mode. Bus reset value: unchanged.
6
DRQPOL
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
5
DAKPOL
Selects DACK2 pin signal polarity (0 = active LOW).
Bus reset value: unchanged.
4
EOTPOL
Selects EOT pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
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